Encoding data within a crossbar memory array

Patent metadata

Field	Value
Publication number	US-2017192711-A1
Application number	US-201415325118-A
Country	US
Kind code	A1
Filing date	Jul 31, 2014
Priority date	Jul 31, 2014
Publication date	Jul 6, 2017
Grant date	—

Abstract

In an example, in a method for encoding data within a crossbar memory array containing cells, bits of input data may be received. The received bits of data may be mapped to the cells in a row of the memory array, in which the cells are to be assigned to one of a low resistance state and a high resistance state. A subset of the mapped bits in the row may be grouped into a word pattern. The word pattern may be arranged such that more low resistance states are mapped to cells that are located closer to a voltage source of the row of the memory array than to cells that are located farther away from the voltage source.

First claim

What is claimed is:

1 . A method for encoding data within a crossbar memory array containing cells, comprising:
receiving, by a processor, bits of input data; mapping the received bits of input data to the cells in a row of the memory array, wherein the cells are to be assigned to one of a low resistance state and a high resistance state according to the mapping; grouping a subset of the mapped bits in the row into a word pattern; and arranging the word pattern such that more low resistance states are assigned to cells that are located closer to a voltage source of the row of the memory array than to cells that are located farther away from the voltage source.

2 . The method of claim 1 , wherein arranging the word pattern further includes flipping the word pattern to one of a big endian arrangement and a little endian arrangement.

3 . The method of claim 2 , wherein flipping the word pattern further includes storing an additional bit in the memory array to indicate whether the word pattern is stored in the big endian arrangement or the little endian arrangement.

4 . The method of claim 3 , wherein storing the additional bit in the memory array further includes storing the additional bit close to the voltage source.

5 . The method of claim 3 . further including:
decoding the word pattern by reverting the word pattern to an original form based on the stored additional bit.

6 . The method of claim 1 , further including storing the bits of input data into corresponding cells of the memory array according to the arranged word pattern.

7 . A data storage apparatus for encoding data within a crossbar memory array containing cells, said data storage apparatus comprising:
a processor; a memory storing machine readable instructions that are to cause the processor to: designate bits of input data to the cells in a row of the memory array. wherein the cells are to be assigned to one of a low resistance state and a high resistance state according to the designation; categorize a portion of the designated bits of input data in the row into a bit pattern; and arrange the bit pattern such more logical “1s” are assigned to cells that are located closer to a voltage source of the row of the memory array than to cells that are located farther away from the voltage source.

8 . The data storage apparatus of claim 7 , wherein to arrange the bit pattern, the machine readable instructions are to cause the processor to flip the bit pattern to one of a big endian arrangement and a little endian arrangement.

9 . The data storage apparatus of claim 8 , wherein to flip the bit pattern, the machine readable instructions are to cause the processor to store an additional bit in the memory array to indicate whether the bit pattern is stored in the big endian arrangement or a little endian arrangement.

10 . The data storage apparatus of claim 8 , wherein to store the additional bit in the memory array, the machine readable instructions are to cause the processor to store the additional bit close to the voltage source.

11 . The data storage apparatus of claim 9 , wherein the machine readable instructions are further to cause the processor to decode the bit pattern by reverting the bit pattern to an original form based on the stored additional bit.

12 . The data storage apparatus of claim 8 , wherein the machine readable instructions are further to cause the processor to store the bits of input data into corresponding cells of the memory array according to the arranged bit pattern.

13 . A non-transitory computer readable medium to encode data within a crossbar memory array containing cells, including machine readable instructions executable by a processor to:
receive bits of input data; map the bits of input data to the cells in a row of the memory array, wherein the cells are assigned to one of a low resistance state and a high resistance state; group a subset of the mapped bits in the row into a word pattern; determine that a majority of low resistance states in the word pattern are mapped to cells that are located farthest away from a voltage source along the row; and flip the word pattern such that a majority of the low resistance states are mapped to cells that are located closer to the voltage source of the row of the memory array.

14 . The non-transitory computer readable medium of claim 13 , wherein to flip the word pattern, the machine readable instructions are executable by the processor to store an additional bit in the memory array to indicate that the word pattern has been flipped, wherein the additional bit is stored close to the voltage source.

15 . The non-transitory computer readable medium of claim 14 , wherein the machine readable instructions are executable by the processor to:
store the bits of input data into corresponding cells of the memory array according to the flipped word pattern; and decode the flipped word pattern by reverting the word pattern to an original form based on the stored additional bit.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Muralimanohar Naveen
• Ordentlich Erik
• Xu Cong

Classifications

• G11C7/1012 Primary

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G11C2213/77

  Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title