In-Cell Touch Panel and Display Device

Patent metadata

Field	Value
Publication number	US-2017192564-A1
Application number	US-201515100129-A
Country	US
Kind code	A1
Filing date	Oct 18, 2015
Priority date	Jun 23, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

An in-cell touch panel and a display device are disclosed, in the in-cell touch panel, each of the self-capacitance electrodes includes a plurality of self-capacitance sub-electrodes which are insulated from each other and connecting lines for connecting the self-capacitance sub-electrodes; an orthographic projection on the first substrate of each self-capacitance sub-electrode does not overlap with an orthographic projection on the first substrate of each gate line; and/or an orthographic projection on the first substrate of each self-capacitance sub-electrode does not overlap with an orthographic projection on the first substrate of each data line. Thus, there is almost no overlapping area between the self-capacitance electrodes and the gate lines and/or there is almost no overlapping area between the self-capacitance electrodes and the data lines, thus there is almost no overlapping capacitance.

First claim

1 . An in-cell touch panel, comprising: a first substrate and a second substrate disposed opposite to each other; a plurality of gate lines and a plurality of data lines which are intersected with and insulated from each other and disposed on one side of the first substrate, which side faces the second substrate; and a plurality of self-capacitance electrodes which are insulated from each other and disposed in a same layer on one side of the first substrate, which side faces the second substrate, or on one side of the second substrate, which side faces the first substrate; wherein,
each of the self-capacitance electrodes comprises a plurality of self-capacitance sub-electrodes which are insulated from each other and connecting lines for connecting the self-capacitance sub-electrodes; an orthographic projection on the first substrate of each self-capacitance sub-electrode does not overlap with an orthographic projection on the first substrate of each gate line; and/or an orthographic projection on the first substrate of each self-capacitance sub-electrode does not overlap with an orthographic projection on the first substrate of each data line.

2 . The touch panel according to claim 1 , wherein, the self-capacitance sub-electrodes are disposed in a matrix;
the connecting lines in each self-capacitance electrode comprise: first connecting lines which are parallel to the gate lines and in one-to-one correspondence with rows of self-capacitance sub-electrodes in the self-capacitance electrode and are configured for connecting each of the self-capacitance sub-electrodes in the corresponding line; and second connecting lines which are parallel to the data lines and are configured for connecting respective rows of self-capacitance sub-electrodes in the self-capacitance electrode.

3 . The touch panel according to claim 2 , wherein, the first connecting lines and the gate lines are disposed in a same layer.

4 . The touch panel according to claims 2 , wherein, the second connecting lines and the data lines are disposed in a same layer.

5 . The touch panel according to claim 2 , further comprising a plurality of pixel units which are disposed in a matrix and are disposed on one side of the first substrate, which side faces the second substrate, each of the pixel units comprising a thin film transistor and a pixel electrode, wherein,
the second connecting lines and the pixel electrodes are disposed in a same layer.

6 . The touch panel according to claim 2 , further comprising a plurality of conductive lines which are in one-to-one correspondence with the self-capacitance electrodes and are configured for electrically connecting the corresponding self-capacitance electrodes and a touch detecting chip, wherein, the first connecting lines in each self-capacitance electrode and the conductive lines corresponding to the self-capacitance electrodes are electrically connected, or the second connecting lines in each self-capacitance electrode and the conductive lines corresponding to the self-capacitance electrodes are electrically connected.

7 . The touch panel according to claim 6 , further comprising a plurality of pixel units which are disposed in a matrix and are disposed on one side of the first substrate, which side faces the second substrate, wherein,
two adjacent columns of pixel units are set as a pixel unit group, and pixel units in different pixel unit groups are different; the pixel units in each pixel unit group are electrically connected with a same data line; each row of pixel units corresponds to two gate lines, and two pixel units which are in each row of pixel units and belong to a same pixel unit group are respectively electrically connected with the two gate lines which correspond to the row of pixel units; and the conductive lines are disposed at intervals each between two adjacent pixel unit groups.

8 . The touch panel according to claim 6 , wherein, the conductive lines and the data lines are disposed in a same layer.

9 . The touch panel according to claim 1 , the self-capacitance sub-electrodes are formed by dividing a common electrode layer which is disposed on one side of the first substrate, which side faces the second substrate.

10 . The touch panel according to claim 1 , wherein, an orthographic projection on the first substrate of each self-capacitance sub-electrode does not overlap with an orthographic projection on the first substrate of each gate line, or an orthographic projection on the first substrate of each self-capacitance sub-electrode does not overlap with an orthographic projection on the first substrate of each gate line and an orthographic projection on the first substrate of each self-capacitance sub-electrode does not overlap with an orthographic projection on the first substrate of each data line;
the self-capacitance sub-electrodes and the gate lines are disposed in a same layer.

11 . A display device, comprising the in-cell touch panel according to claim 1 .

12 . The touch panel according to claim 3 , wherein, the second connecting lines and the data lines are disposed in a same layer.

13 . The touch panel according to claim 3 , further comprising a plurality of pixel units which are disposed in a matrix and are disposed on one side of the first substrate, which side faces the second substrate, each of the pixel units comprising a thin film transistor and a pixel electrode, wherein,
the second connecting lines and the pixel electrodes are disposed in a same layer.

14 . The touch panel according to claim 3 , further comprising a plurality of conductive lines which are in one-to-one correspondence with the self-capacitance electrodes and are configured for electrically connecting the corresponding self-capacitance electrodes and a touch detecting chip, wherein,
the first connecting lines in each self-capacitance electrode and the conductive lines corresponding to the self-capacitance electrodes are electrically connected, or the second connecting lines in each self-capacitance electrode and the conductive lines corresponding to the self-capacitance electrodes are electrically connected.

15 . The touch panel according to claim 4 , further comprising a plurality of conductive lines which are in one-to-one correspondence with the self-capacitance electrodes and are configured for electrically connecting the corresponding self-capacitance electrodes and a touch detecting chip, wherein,
the first connecting lines in each self-capacitance electrode and the conductive lines corresponding to the self-capacitance electrodes are electrically connected, or the second connecting lines in each self-capacitance electrode and the conductive lines corresponding to the self-capacitance electrodes are electrically connected.

16 . The touch panel according to claim 5 , further comprising a plurality of conductive lines which are in one-to-one correspondence with the self-capacitance electrodes and are configured for electrically connecting the corresponding self-capacitance electrodes and a touch detecting chip, wherein,
the first connecting lines in each self-capacitance electrode and the conductive lines corresponding to the self-capacitance electrodes are electrically connected, or the second connecting lines in each self-capacitance electrode and the conductive lines corresponding to the self-capacitance electrodes are electrically connected.

17 . The touch panel according to claim 7 , wherein, the conductive lines and the data lines are disposed in a same layer.

18 . The touch panel according to claim 2 , wherein, the se

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Li Changfeng
• Dong Xue
• Wang Haisheng
• Chen Xiaochuan
• Wang Lei
• Liu Yingming
• Yang Shengji
• Ding Xiaoliang
• Zhao Weijie
• Liu Wei
• Liu Hongjuan
• Liu Jiantao
• Xu Rui

Classifications

• G06F2203/04111

  Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate · CPC title

• G06F3/044

  by capacitive means · CPC title

• G02F1/13338

  Input devices, e.g. touch panels · CPC title

• G06F2203/04103

  Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices · CPC title

• G06F3/0412 Primary

  Digitisers structurally integrated in a display · CPC title