Adaptive power capping in a chip

Patent metadata

Field	Value
Publication number	US-2017192477-A1
Application number	US-201614986944-A
Country	US
Kind code	A1
Filing date	Jan 4, 2016
Priority date	Jan 4, 2016
Publication date	Jul 6, 2017
Grant date	—

Abstract

Adaptive power capping in a chip that includes a plurality of cores in a processing system is provided. An active power demand for the chip is dynamically determined based on observed events of the cores. An average temperature of the chip is computed using one or more on-chip thermal sensors in the cores to estimate leakage power of the chip. A power capping threshold that incorporates the estimate of leakage power is determined based on the average temperature of the chip. Power capping is performed by throttling the cores based on determining that the active power demand for the chip exceeds the power capping threshold.

First claim

What is claimed is:

1 . A method of adaptive power capping in a chip comprising a plurality of cores in a processing system, the method comprising:
dynamically determining an active power demand for the chip based on observed events of the cores; computing an average temperature of the chip using one or more on-chip thermal sensors in the cores to estimate leakage power of the chip; determining a power capping threshold that incorporates the estimate of leakage power based on the average temperature of the chip; and throttling the cores to perform power capping based on determining that the active power demand for the chip exceeds the power capping threshold.

2 . The method of claim 1 , wherein the power capping threshold is further based on vital product data of the chip that includes leakage current at known temperature and voltage, and the method further comprising:
un-throttling the cores to remove the throttling based determining that the active power demand for the chip does not exceed the power capping threshold.

3 . The method of claim 1 , wherein the throttling of the cores is further based on detecting a redundancy state of a redundant power system of the processing system.

4 . The method of claim 1 , wherein determining the power capping threshold further comprises:
using the average temperature of the chip to index into a power capping table comprising a plurality of power capping thresholds that are predetermined based on a leakage power model of a reference chip.

5 . The method of claim 1 , wherein the active power demand for the chip is determined at a higher frequency than the average temperature of the chip is computed.

6 . The method of claim 1 , wherein an on-chip micro-controller computes a total active power demand and controls the throttling of the cores.

7 . The method of claim 1 , wherein an on-chip micro-controller determines the power capping threshold and writes the power capping threshold to a chip-level register, and the on-chip logic circuits compute a total active power demand from the cores and control the throttling of the cores.

8 . The method of claim 1 , wherein throttling the cores comprises selectively inserting idle cycles at each of the cores.

9 . A processing system comprising:
a redundant power system; and a processor chip comprising a plurality of cores, the processor chip operable to perform a method comprising:
dynamically determining an active power demand for the processor chip based on observed events of the cores;
computing an average temperature of the processor chip using one or more on-chip thermal sensors in the cores to estimate leakage power of the processor chip;
determining a power capping threshold that incorporates the estimate of leakage power based on the average temperature of the processor chip; and
throttling the cores to perform power capping based on detecting a redundancy state of the redundant power system and determining that the active power demand for the processor chip exceeds the power capping threshold.

10 . The processing system of claim 9 , wherein the power capping threshold is further based on vital product data of the chip that includes leakage current at known temperature and voltage, and the cores are un-throttled to remove the throttling based determining that the active power demand for the processor chip does not exceed the power capping threshold.

11 . The processing system of claim 9 , wherein determining the power capping threshold further comprises:
using the average temperature of the processor chip to index into a power capping table comprising a plurality of power capping thresholds that are predetermined based on a leakage power model of a reference chip.

12 . The processing system of claim 9 , wherein the active power demand for the processor chip is determined at a higher frequency than the average temperature of the processor chip is computed.

13 . The processing system of claim 9 , wherein an on-chip micro-controller computes a total active power demand and controls the throttling of the cores.

14 . The processing system of claim 9 , wherein an on-chip micro-controller determines the power capping threshold and writes the power capping threshold to a chip-level register, and the on-chip logic circuits compute a total active power demand from the cores and control the throttling of the cores.

15 . The processing system of claim 9 , wherein throttling the cores comprises selectively inserting idle cycles at each of the cores.

16 . A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor chip to cause the processor chip to:
dynamically determine an active power demand for the processor chip based on observed events of the cores; compute an average temperature of the processor chip using one or more on-chip thermal sensors in the cores to estimate leakage power of the processor chip; determine a power capping threshold that incorporates the estimate of leakage power based on the average temperature of the processor chip; and throttle the cores to perform power capping based on determining that the active power demand for the processor chip exceeds the power capping threshold.

17 . The computer program product of claim 16 , wherein the cores are un-throttled to remove the throttling based determining that the active power demand for the processor chip does not exceed the power capping threshold.

18 . The computer program product of claim 16 , wherein the throttling of the cores is further based on detecting a redundancy state of a redundant power system of the processing system and wherein determining the power capping threshold further comprises using the average temperature of the processor chip to index into a power capping table comprising a plurality of power capping thresholds that are predetermined based on a leakage power model of a reference chip.

19 . The computer program product of claim 16 , wherein an on-chip micro-controller computes a total active power demand and controls the throttling of the cores.

20 . The computer program product of claim 16 , wherein an on-chip micro-controller determines the power capping threshold and writes the power capping threshold to a chip-level register, and the on-chip logic circuits compute a total active power demand from the cores and control the throttling of the cores.

Assignees

• IBM

Inventors

• Lefurgy Charles R
• Lobo Preetham M
• Rizzolo Richard F
• Allen-Ware Malcolm S
• Webel Tobias

Classifications

• G06F1/28 Primary

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F9/44

  Arrangements for executing specific programs · CPC title

• G06F1/324

  by lowering clock frequency · CPC title