Array Substrate and Method of Manufacturing the Same, and Display Device

Patent metadata

Field	Value
Publication number	US-2017192319-A1
Application number	US-201615253095-A
Country	US
Kind code	A1
Filing date	Aug 31, 2016
Priority date	Jan 6, 2016
Publication date	Jul 6, 2017
Grant date	—

Abstract

An array substrate and a method of manufacturing the same, and a display device are disclosed. The array substrate includes a base substrate; a pixel electrode, a thin film transistor, a gate line and a data line that are provided on the base substrate; and an electrostatic shielding layer provided on the base substrate. The electrostatic shielding layer is configured for electrostatic protection during production of the array substrate.

First claim

What is claimed is:

1 . An array substrate, comprising:
a base substrate, a pixel electrode, a thin film transistor, a gate line and a data line that are provided on the base substrate, and an electrostatic shielding layer provided on the base substrate, wherein the electrostatic shielding layer is configured for electrostatic protection during production of the array substrate.

2 . The array substrate according to claim 1 , further comprising an insulation layer that is provided on a side of the electrostatic shielding layer away from the base substrate, wherein the thin film transistor, the gate line and the data line are all provided on a side of the insulation layer away from the electrostatic shielding layer.

3 . The array substrate according to claim 2 , wherein the electrostatic shielding layer comprises a plurality of longitudinal portions and a plurality of transverse portions, and the plurality of longitudinal portions and the plurality of transverse portions intersect to form a grid pattern.

4 . The array substrate according to claim 3 , wherein the array substrate comprises a plurality of gate lines and a plurality of data lines, a projection of the plurality of longitudinal portions on the array substrate is provided within a projection of the data lines on the array substrate, and a projection of the plurality of transverse portions on the array substrate is provided within a projection of the gate lines on the array substrate.

5 . The array substrate according to claim 3 , wherein the electrostatic shielding layer and the pixel electrode layer are disposed in a same layer and are made of a same material.

6 . The array substrate according to claim 1 , further comprising a ground circuit, wherein the electrostatic shielding layer is electrically connected to the ground circuit.

7 . A display device, comprising the array substrate according to claim 1 .

8 . The display device according to claim 7 , wherein the display device is a liquid crystal display device, an organic light-emitting diode display device, or an e-ink display device.

9 . A method of manufacturing an array substrate, comprising:
forming a pixel electrode, a thin film transistor, a gate line and a data line on a base substrate, and forming an electrostatic shielding layer on the base substrate, the electrostatic shielding layer being configured for electrostatic protection during production of the array substrate.

10 . The method of manufacturing an array substrate according to claim 9 , wherein forming of the thin film transistor, the gate line and the data line is conducted after forming of the electrostatic shielding layer; and the method further comprises:
forming an insulation layer on the electrostatic shielding layer after forming of the electrostatic shielding layer and prior to forming of the thin film transistor, the gate line and the data line.

11 . The method of manufacturing an array substrate according to claim 10 , wherein the electrostatic shielding layer comprises a plurality of longitudinal portions and a plurality of transverse portions, and the plurality of longitudinal portions and the plurality of transverse portions intersect to form a grid pattern.

12 . The method of manufacturing an array substrate according to claim 11 , wherein a plurality of gate lines and a plurality of data lines are formed, a projection of the plurality of longitudinal portions on the array substrate is provided within a projection of the data lines on the array substrate, and a projection of the plurality of transverse portions on the array substrate is provided within a projection of the gate lines on the array substrate.

13 . The method of manufacturing an array substrate according to claim 11 , wherein the electrostatic shielding layer and the pixel electrode layer are simultaneously formed in a patterning process.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Zhang Pengju
• Li Xin
• Li Bin
• Zhao Detao
• Yuan Xuchen

Classifications

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/136204 Primary

  Arrangements to prevent high voltage or static electricity failures · CPC title

• G02F1/134309

  characterised by their geometrical arrangement · CPC title

• H01L27/3272

  Electricity · mapped topic