PVT Compensation Scheme for Output Buffers
US-2015372679-A1 · Dec 24, 2015 · US
US2017168514A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2017168514-A1 |
| Application number | US-201514963790-A |
| Country | US |
| Kind code | A1 |
| Filing date | Dec 9, 2015 |
| Priority date | Dec 9, 2015 |
| Publication date | Jun 15, 2017 |
| Grant date | — |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
In one embodiment, a temperature management system comprises a plurality of temperature sensors on a chip, and a temperature manager. The temperature manager is configured to receive a plurality of temperature readings from the temperature sensors, to determine a plurality of power values based on the temperature readings, to determine a plurality of temperature values based on the determined power values, the determined temperature values corresponding to a plurality of different locations on the chip, and to estimate a temperature of a hotspot on the chip based on the determined temperature values.
Opening claim text (preview).
What is claimed is: 1 . A temperature management system, comprising: a plurality of temperature sensors on a chip; and a temperature manager configured to receive a plurality of temperature readings from the temperature sensors, to determine a plurality of power values based on the temperature readings, to determine a plurality of temperature values based on the determined power values, the determined temperature values corresponding to a plurality of different locations on the chip, and to estimate a temperature of a hotspot on the chip based on the determined temperature values. 2 . The system of claim 1 , wherein the temperature manager is configured to estimate the temperature of the hotspot based on a largest one of the determined temperature values. 3 . The system of claim 2 , wherein the temperature manager is configured to estimate a location of the hotspot based on the location corresponding to the largest one of the determined temperature values. 4 . The system of claim 1 , wherein each of the power values corresponds to power at a respective one of a plurality of blocks on the chip. 5 . The system of claim 4 , wherein the blocks include one or more processors. 6 . The system of claim 1 , wherein the temperature manager is configured to determine the power values using an inverse of a first influence coefficient matrix comprising a first plurality of coefficients, each of the first plurality of coefficients relating power at a respective one of a plurality of blocks on the chip to a temperature change at a respective one of the temperature sensors. 7 . The system of claim 6 , wherein the temperature manager is configured to determine the temperature values using a second influence coefficient matrix comprising a second plurality of coefficients, each of the second plurality of coefficients relating power at a respective one of the blocks on the chip to a temperature change at a respective one of the locations on the chip. 8 . The system of claim 1 , wherein the temperature manager is configured to compare the estimated temperature of the hotspot to a temperature threshold, and to initiate temperature mitigation if the estimated temperature of the hotspot exceeds the temperature threshold. 9 . The system of claim 8 , wherein the temperature manager is configured to initiate temperature mitigation by commanding a clock source to reduce a frequency of a clock signal, commanding a power source to reduce a supply voltage, or both. 10 . A method for managing temperature, comprising: receiving temperature readings from a plurality of temperature sensors on a chip; determining a plurality of power values based on the temperature readings; determining a plurality of temperature values based on the determined power values, the determined temperature values corresponding to a plurality of different locations on the chip; and estimating a temperature of a hotspot on the chip based on the determined temperature values. 11 . The method of claim 10 , wherein estimating the temperature of the hotspot comprises determining a largest one of the determined temperature values. 12 . The method of claim 11 , further comprising estimating a location of the hotspot based on the location corresponding to the largest one of the determined temperature values. 13 . The method of claim 10 , wherein each of the power values corresponds to power at a respective one of a plurality of blocks on the chip. 14 . The method of claim 13 , wherein the blocks include one or more processors. 15 . The method of claim 10 , wherein determining the power values comprises determining the power values using an inverse of a first influence coefficient matrix comprising a first plurality of coefficients, each of the first plurality of coefficients relating power at a respective one of a plurality of blocks on the chip to a temperature change at a respective one of the temperature sensors. 16 . The method of claim 15 , wherein determining the temperature values comprises determining the temperature values using a second influence coefficient matrix comprising a second plurality of coefficients, each of the second plurality of coefficients relating power at a respective one of the blocks on the chip to a temperature change at a respective one of the locations on the chip. 17 . The method of claim 10 , further comprising: comparing the estimated temperature of the hotspot to a temperature threshold; initiating temperature mitigation if the estimated temperature of the hotspot exceeds the temperature threshold. 18 . The method of claim 17 , wherein initiating temperature mitigation comprises commanding a clock source to reduce a frequency of a clock signal, commanding a power source to reduce a supply voltage, or both. 19 . An apparatus for managing temperature, comprising: means for receiving temperature readings from a plurality of temperature sensors on a chip; means for determining a plurality of power values based on the temperature readings; means for determining a plurality of temperature values based on the determined power values, the determined temperature values corresponding to a plurality of different locations on the chip; and means for estimating a temperature of a hotspot on the chip based on the determined temperature values. 20 . The apparatus of claim 19 , wherein the means for estimating the temperature of the hotspot comprises means for determining a largest one of the determined temperature values. 21 . The apparatus of claim 20 , further comprising means for estimating a location of the hotspot based on the location corresponding to the largest one of the determined temperature values. 22 . The apparatus of claim 19 , wherein each of the power values corresponds to power at a respective one of a plurality of blocks on the chip. 23 . The apparatus of claim 22 , wherein the blocks include one or more processors. 24 . The apparatus of claim 19 , wherein the means for determining the power values comprises means for determining the power values using an inverse of a first influence coefficient matrix comprising a first plurality of coefficients, each of the first plurality of coefficients relating power at a respective one of a plurality of blocks on the chip to a temperature change at a respective one of the temperature sensors. 25 . The apparatus of claim 24 , wherein the means for determining the temperature values comprises means for determining the temperature values using a second influence coefficient matrix comprising a second plurality of coefficients, each of the second plurality of coefficients relating power at a respective one of the blocks on the chip to a temperature change at a respective one of the locations on the chip. 26 . The apparatus of claim 19 , further comprising: means for comparing the estimated temperature of the hotspot to a temperature threshold; means for initiating temperature mitigation if the estimated temperature of the hotspot exceeds the temperature threshold. 27 . The apparatus of claim 26 , wherein the means for initiating temperature mitigation comprises means for commanding a clock source to reduce a frequency of a clock signal, means for commanding a power source to reduce a supply voltage, or both.
Thermometers specially adapted for specific purposes · CPC title
Sources providing an output which depends on temperature · CPC title
Monitoring of events, devices or parameters that trigger a change in power modality · CPC title
comprising thermal management · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.