Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium

Patent metadata

Field	Value
Publication number	US-2017162498-A1
Application number	US-201715441595-A
Country	US
Kind code	A1
Filing date	Feb 24, 2017
Priority date	Mar 17, 2000
Publication date	Jun 8, 2017
Grant date	—

Abstract

A multilayer semiconductor device includes first wirings extending in a first direction adjacent to each other in a second direction. Dummy wirings are arranged between the first wirings and a second wiring at crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction. The dummy wirings have a first dummy wiring, a second dummy wiring, a third dummy wiring, a fourth dummy wiring, and a fifth dummy wiring. When the dummy wirings are rotated around a center of the first dummy wiring through 90 degrees, centers of the second, third, fourth, and fifth dummy wirings are aligned with centers of the fourth, fifth, third, and second dummy wirings prior to being rotated.

First claim

What is claimed is:

1 . A multilayer semiconductor device comprising:
a plurality of first wirings extending in a first direction, the plurality of first wirings are arranged adjacent to each other in a second direction on a layer level; a second wiring that is apart from the plurality of first wirings in the second direction on the layer level; and a plurality of dummy wirings arranged between the plurality of first wirings and the second wiring on the layer level, the plurality of dummy wirings are arranged at a plurality of crossing points between first virtual linear lines extending in a third direction and second virtual linear lines extending in a fourth direction, wherein: the third direction and the fourth direction are neither parallel nor orthogonal to the first direction and the second direction, the plurality of dummy wirings having: a first dummy wiring; a second dummy wiring that is directly adjacent to the first dummy wiring on one of the first virtual lines in the third direction; a third dummy wiring that is directly adjacent to the first dummy wiring on the one of the first virtual lines in a direction opposite of the third direction; a fourth dummy wiring that is directly adjacent to the first dummy wiring on one of the second virtual lines in the fourth direction; and a fifth dummy wiring that is directly adjacent to the first dummy wiring on the one of the second virtual lines in a direction opposite of the fourth direction, wherein the first, second, third, fourth, and fifth dummy wirings are arranged such that when the second dummy wiring, the third dummy wiring, the fourth dummy wiring and the fifth dummy wiring are rotated around a center of the first dummy wiring through 90 degrees, centers of each of the second dummy wiring, the third dummy wiring, the fourth dummy wiring and the fifth dummy wiring are aligned with centers of the fourth dummy wiring, the fifth dummy wiring, the third dummy wiring and the second dummy wiring, respectively, prior to being rotated.

2 . The multilayer semiconductor device according to claim 1 , wherein the dummy wirings are square-shaped in a plan view.

3 . The multilayer semiconductor device according to claim 1 , wherein the dummy wirings have a square shape in a plan view.

4 . The multilayer semiconductor device according to claim 1 ,
wherein each of the dummy wirings has a first side, a second side parallel to the first side, a third side perpendicular to the first side and a fourth side parallel to the third side, and wherein the first side, the second side, the third side and the fourth side are the same length.

5 . The multilayer semiconductor device according to claim 1 , wherein:
a center of the first dummy wiring, a center of the second dummy wiring, and a center of the third dummy wiring are disposed on one of the first virtual linear lines; and the center of the first dummy wiring, a center of the fourth dummy wiring, and a center of the fifth dummy wiring are disposed on one of the second virtual linear lines.

6 . The multilayer semiconductor device of claim 5 , wherein the one of the second virtual linear lines is perpendicular to the one of the first virtual linear lines.

7 . The multilayer semiconductor device according to claim 1 , wherein an angle between the first virtual linear lines and the first direction is the same as an angle between the second virtual linear lines and the second direction.

8 . The multilayer semiconductor device according to claim 1 , wherein an angle between the first virtual linear lines and the first direction is between 2 and 40°.

9 . The multilayer semiconductor device according to claim 1 , wherein an angle between the first virtual linear lines and the first direction is between 15 and 25°.

10 . The multilayer semiconductor device according to claim 1 , wherein an angle between the second virtual linear lines and the second direction is between 2 and 40°.

11 . The multilayer semiconductor device according to claim 1 , wherein an angle between the second virtual linear lines and the second direction is between 15 and 25°.

12 . The multilayer semiconductor device of claim 1 , wherein the second virtual linear lines are perpendicular to the first virtual linear lines.

Assignees

• Seiko Epson Corp

Inventors

• Mori Katsumi
• Kawahara Kei
• Kasuya Yoshikazu

Classifications

• H10W20/092

  by smoothing the dielectric parts · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title