Memory-aware matrix factorization

Patent metadata

Field	Value
Publication number	US-2017154404-A1
Application number	US-201715431986-A
Country	US
Kind code	A1
Filing date	Feb 14, 2017
Priority date	Jun 18, 2015
Publication date	Jun 1, 2017
Grant date	—

Abstract

Embodiments include method, systems and computer program products for performing memory-aware matrix factorization on a graphics processing unit. Aspects include determining one or more types of memory on the graphics processing unit and determining one or more characteristics of each of the one or more types of memory. Aspects also include assigning each of a plurality of memory accesses of a matrix factorization algorithm to one of the one or more types of memory based on the one or more characteristics and executing the matrix factorization algorithm on the graphics processing unit.

First claim

What is claimed is:

1 . A method for performing memory-aware matrix factorization on a graphics processing unit, the method comprising:
determining one or more types of memory on the graphics processing unit; determining one or more characteristics of each of the one or more types of memory; assigning each of a plurality of memory accesses of a matrix factorization algorithm to one of the one or more types of memory based on the one or more characteristics; and executing the matrix factorization algorithm on the graphics processing unit.

2 . The method of claim 1 , wherein the assignment of the plurality of memory accesses is configured to reduce discontiguous memory access.

3 . The method of claim 1 , wherein the one or more types of memory include a register memory, a cache memory and a global memory.

4 . The method of claim 3 , wherein the assignment of the plurality of memory accesses is configured to store hotspot variables in the cache memory.

5 . The method of claim 1 , wherein the characteristics include at least one of a memory size, an access latency, and a read/write permission.

6 . The method of claim 3 , wherein the cache memory includes a texture memory that is used to store cached entries from the global memory.

7 . The method of claim 3 , wherein the cache memory includes a texture memory that is used to cache read-only entries from the global memory.

Assignees

• IBM

Inventors

• Cao Liangliang
• Fong Liana L
• Tan Wei

Classifications

• G06F17/16

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G06F2212/60

  Details of cache memory · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F12/0877

  Cache access modes · CPC title

• G06T1/60 Primary

  Memory management · CPC title