Secondary-Side Dynamic Load Detection and Communication Device
US-2016028313-A1 · Jan 28, 2016 · US
US2017149233A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2017149233-A1 |
| Application number | US-201514946033-A |
| Country | US |
| Kind code | A1 |
| Filing date | Nov 19, 2015 |
| Priority date | Nov 19, 2015 |
| Publication date | May 25, 2017 |
| Grant date | — |
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A high side output driver includes a controller capable of operating the high side output driver in a charging mode by outputting a pulse width modulated voltage signal. The on time of the pulse width modulated voltage signal is less than a minimum value of a blank time range of the high side output driver.
Opening claim text (preview).
1 . A controller for operating a high side output driver comprising: a first control logic configured to operate a high side output driver in a charging mode by outputting a pulse width modulated voltage signal, the on time of the pulse width modulated voltage signal being less than a minimum value of a blank time range of the high side output driver. 2 . The controller of claim 1 , further comprising: a second control logic configured to set the blank time range of the high side driver to a maximum blank time range while operating the high side output driver in an initialization mode. 3 . The controller of claim 2 , wherein operating the high side output driver in the initialization mode includes setting an on time of the pulse width modulated voltage signal to less than the minimum value of the maximum blank time range. 4 . The controller of claim 1 , wherein the control logic is further configured to transition from the charging mode to a standard operations mode by increasing the duty cycle of the pulse width modulated voltage signal such that the on time of the pulse width modulated voltage exceeds the minimum value of the maximum blank time range. 5 . The controller of claim 4 , wherein the duty cycle of the voltage signal during the standard operations mode is 100%. 6 . The controller of claim 4 , wherein the transition occurs in response to a load reaching a fully charged state. 7 . The controller of claim 4 , wherein the transition occurs in response to a charge time (t charge ) elapsing. 8 . The controller of claim 1 , wherein the current at the voltage output of the high side output driver is current limited such that the current at the voltage output is below an excess current threshold during the standard operations mode. 9 . The controller of claim 8 , wherein the excess current threshold is above an expected maximum current. 10 . The controller of claim 1 , wherein an off time of the voltage output is configured such that a charging load discharges less in the off time than is charged in the on time. 11 . The controller of claim 1 , where the controller is a programmable controller including a memory, the memory including instructions operable to cause the high side output driver to enter an initialization mode, configure the high side driver for a charging mode, enter a charging mode, and transition to a standard operations mode. 12 . The controller of claim 1 , further comprising: a second control logic configured to set a blank time range of the high side driver to a maximum blank time range while operating the high side output driver in an initialization mode, and configured to set an on time of the pulse width modulated voltage signal to less than the minimum value of the maximum blank time range. 13 . A high side output driver comprising: a driver circuitry having an output circuit configured to output a voltage, and a current limiting circuit connecting the output circuit to a voltage output; and a controller controllably coupled to the driver circuitry and including a processor and a memory, the memory storing instructions configured to cause the processor to perform the steps of: initializing the high side output driver; operating the high side output driver in a charging mode; and operating the high side output driver in a standard operations mode. 14 . The high side driver of claim 13 , wherein the output circuit includes a transistor connecting a voltage source to an input of the current limiting circuit while in a closed state, and a control input connected to the controller. 15 . The high side driver of claim 13 , wherein the controller further includes a fault detector. 16 . A method for detecting a fault condition in a high side output driver comprising: initializing the high side output driver by at least setting a charge time; placing the high side driver in a charging mode of operations, and operating the high side driver in the charging mode for at least the charge time; comparing an output current of the high side output driver against a fault current threshold when said charge time has elapsed; incrementing a fault counter in response to a fault being detected; returning to the step of placing the high side driver in the charging mode of operations in response to the fault counter being less than or equal to a preset value. 17 . The method of claim 16 , further comprising determining that a fault exists in response to said fault counter exceeding a preset value, and disabling an output of the high side output driver. 18 . The method of claim 16 , further comprising determining that no fault exists in response to the output current of the high side output driver being less than the fault current threshold when said charge time has elapsed. 19 . The method of claim 16 , further comprising increasing the duration of the charge time by a preset magnitude in response to the output current exceeding the fault current threshold.
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