Polymer on graphene

US2017141202A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2017141202-A1
Application numberUS-201715419719-A
CountryUS
Kind codeA1
Filing dateJan 30, 2017
Priority dateNov 25, 2013
Publication dateMay 18, 2017
Grant date

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A top-gated graphene field effect transistor can be fabricated by forming a layer of graphene on a substrate, and applying an electrochemical deposition process to deposit a layer of dielectric polymer on the graphene layer. An electric potential between the graphene layer and a reference electrode is cycled between a lower potential and a higher potential. A top gate is formed above the polymer.

First claim

Opening claim text (preview).

What is claimed is: 1 . A graphene transistor comprising: a substrate; a layer of graphene on the substrate; a layer of dielectric polymer comprising poly(phenylene oxide) on the graphene layer; and a top gate above the polymer. 2 . The transistor of claim 1 in which the graphene layer is patterned to form a channel, and the transistor further comprises drain and source electrodes that are electrically coupled to the graphene. 3 . The transistor of claim 1 , comprising a layer of second dielectric material on the dielectric polymer layer, the second dielectric material having a dielectric constant that is higher than the dielectric constant of the polymer. 4 . The transistor of claim 1 in which the dielectric polymer layer has a thickness that is less than 10 nm. 5 . An apparatus comprising: a substrate; a layer of two-dimensional material on the substrate; and a layer of polymer on the graphene, the polymer comprising poly(phenylene oxide). 6 . The apparatus of claim 5 in which the two-dimensional material comprises graphene. 7 . The apparatus of claim 6 comprising a drain electrode, a source electrode, and a top gate, in which the layer of graphene is disposed between the drain and source electrodes and is configured to function as a channel, and the top gate is disposed above the layer of polymer. 8 . The apparatus of claim 7 , comprising a dielectric layer disposed between the polymer layer and the top gate. 9 . The apparatus of claim 8 in which the dielectric layer comprises a dielectric that has a dielectric constant that is higher than the dielectric constant of the polymer. 10 . The apparatus of claim 6 in which the layer of graphene comprises a monolayer of graphene. 11 . The apparatus of claim 5 in which the polymer layer has a thickness in a range between 500 nm to 1 μm. 12 . The apparatus of claim 5 in which the polymer layer has a thickness in a range from 100 nm to 500 nm. 13 . The apparatus of claim 5 in which the polymer layer has a thickness in a range from 10 nm to 100 nm. 14 . The apparatus of claim 5 in which the polymer layer has a thickness less than 10 nm. 15 . The apparatus of claim 5 in which the two-dimensional material comprises phosphorene. 16 . The apparatus of claim 15 in which the polymer layer covers the phosphorene to prevent oxidation of the phosphorene. 17 . An apparatus comprising: a substrate; a layer of two-dimensional material on the substrate, in which the two-dimensional material is at least one of a conducting or a semiconducting material; and a dielectric polymer formed on the layer of two-dimensional material by applying an electrochemical deposition process to deposit the dielectric polymer on the two-dimensional material, in which a rate of deposition of the dielectric polymer at a given location of the two-dimensional material decreases as a thickness of the dielectric polymer layer increases. 18 . The apparatus of claim 17 in which the dielectric polymer comprises poly(phenylene oxide).

Assignees

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Classifications

  • Carbon, e.g. diamond-like carbon · CPC title

  • being conductive materials, e.g. metallic silicides · CPC title

  • using chemical vapour deposition [CVD] · CPC title

  • Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating · CPC title

  • carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC · CPC title

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What does patent US2017141202A1 cover?
A top-gated graphene field effect transistor can be fabricated by forming a layer of graphene on a substrate, and applying an electrochemical deposition process to deposit a layer of dielectric polymer on the graphene layer. An electric potential between the graphene layer and a reference electrode is cycled between a lower potential and a higher potential. A top gate is formed above the polymer.
Who is the assignee on this patent?
Nutech Ventures
What technology area does this patent fall under?
Primary CPC classification H01L29/51. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu May 18 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).