Semiconductor device

Patent metadata

Field	Value
Publication number	US-2017141086-A1
Application number	US-201715420410-A
Country	US
Kind code	A1
Filing date	Jan 31, 2017
Priority date	Sep 30, 2014
Publication date	May 18, 2017
Grant date	—

Abstract

A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.

First claim

What is claimed is:

1 . An electronic device comprising:
a substrate having a top surface and a bottom surface opposite to the top surface, a shape in a plan view of the top surface being comprised of a rectangle having a first long side, a second long side, a first short side and a second short side, a first metal pattern formed on the top surface of the substrate; a second metal pattern formed on the top surface of the substrate, and spaced apart from the first metal pattern; a third metal pattern formed on the top surface of the substrate, and spaced apart from the first and second metal patterns; a fourth metal pattern formed on the top surface of the substrate, and spaced apart from the first, second and third metal patterns; a first semiconductor chip mounted on a first region in a surface of the first metal pattern via a first bonding material; a second semiconductor chip mounted on a first region in a surface of the second metal pattern via a second bonding material; a first terminal mounted on a first region in a surface of the third metal pattern via a third bonding material, and connected with the third metal pattern via the third bonding material; a second terminal mounted on a first region in a surface of the fourth metal pattern via a fourth bonding material, and connected with the fourth terminal via the fourth bonding material; a cover member adhered to the substrate, and covering a second region in the surface of the first metal pattern, which is not overlapped with the first semiconductor chip and the first bonding material, a second region in the surface the second metal pattern, which is not overlapped with the second semiconductor chip and the second bonding material, a second region in the surface of the third metal pattern, which is not overlapped with the first terminal and the third bonding material, a second region in the surface of the fourth metal pattern, which is not overlapped with the second terminal and the fourth bonding material, the first semiconductor chip and the second semiconductor chip; and a sealing material sealing the first semiconductor chip, the second semiconductor chip, a part of the first terminal and a part of the second terminal, wherein, in the plan view, the first region the first metal pattern, the first region of the second metal pattern, the first region of the third metal pattern and the first region of the fourth metal pattern are arranged along the short side of the substrate, wherein, in the plan view, the first region of each of the first and second metal patterns is located between the third metal pattern and the fourth metal pattern, wherein, in the plan view, the first region of the first metal pattern is located between the third metal pattern and the first region of the second metal pattern, wherein no pattern is located between the third metal pattern and the first long side of the substrate, and located between the fourth metal pattern and the second long side, and wherein dimples are formed in each of the second region of the third metal pattern and the second region of the fourth metal pattern, but not formed in each of the first region of the first metal pattern, the first region of the second metal pattern, the first region of the third metal pattern and the first region of the fourth metal pattern.

2 . The semiconductor device according to claim 1 ,
wherein, in the plan view, first dimples of the dimples, which are formed in the second region of the third metal pattern, are arranged along a side of the surface of the third metal pattern, and wherein, in plan view, second dimples of the dimples, which are formed in the second region of the fourth metal pattern, are arranged along a side of the surface of the fourth metal pattern.

3 . The semiconductor device according to claim 1 ,
wherein the first semiconductor chip has a first transistor, a first upper surface, a first gate electrode formed on the first upper surface, a first emitter electrode formed on the first upper surface, a first lower surface opposite to the first upper surface, and a first collector electrode formed on the first lower surface, wherein the first bonding material is comprised of solder, wherein the first collector electrode of the first semiconductor chip is electrically connected with the first metal pattern via the first bonding material, and wherein third dimples of the dimples are formed in the second region of the first metal pattern, and arranged along a side of the surface of the first metal pattern in the plan view.

4 . The semiconductor device according to claim 3 ,
wherein the second semiconductor chip has a second transistor, a second upper surface, a second gate electrode formed on the second upper surface, a second emitter electrode formed on the second upper surface, a second lower surface opposite to the second upper surface, and a second collector electrode formed on the second lower surface, and wherein the second bonding material is comprised of solder, and wherein the first emitter electrode of the first semiconductor chip is electrically connected with the second collector electrode of the second semiconductor chip via a first wire, the second metal pattern and the second bonding material.

5 . The semiconductor device according to claim 4 ,
wherein fourth dimples of the dimples are formed in the second region of the second metal pattern, and arranged along a side of the surface of the fourth metal pattern in the plan view.

6 . The semiconductor device according to claim 4 ,
wherein a fifth metal pattern is formed on the top surface of the substrate, and located between the second metal pattern and the fourth metal pattern in the plan view, and wherein the second emitter electrode of the second semiconductor chip is electrically connected with the fifth metal pattern via a second wire.

7 . The semiconductor device according to claim 6 , wherein fifth dimples of the dimples are formed on a surface of the fifth metal pattern, and arranged along a side of the surface of the fifth metal pattern in the plan view.

Assignees

• Renesas Electronics Corp

Inventors

• Funatsu Katsuhiko
• Sato Yukihiro
• Kanazawa Takamitsu
• Koido Masahiro
• Taya Hiroyoshi

Classifications

• H02S40/32

  comprising DC/AC inverter means associated with the PV module itself, e.g. AC modules · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W76/60

  Seals · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title