Self-Aligned Dual-Metal Silicide and Germanide Formation

Patent metadata

Field	Value
Publication number	US-2017140942-A1
Application number	US-201715419943-A
Country	US
Kind code	A1
Filing date	Jan 30, 2017
Priority date	Aug 9, 2013
Publication date	May 18, 2017
Grant date	—

Abstract

A device having an epitaxial region and dual metal-semiconductor alloy surfaces is provided. The epitaxial region includes an upward facing facet and a downward facing facet. The upward facing facet has a first metal-semiconductor alloy surface and the downward facing facet has a second metal-semiconductor alloy surface, wherein the first metal-semiconductor alloy is different than the second metal-semiconductor alloy.

First claim

What is claimed is:

1 . A method comprising:
growing a first epitaxy semiconductor region on a wafer, wherein the first epitaxy semiconductor region comprises an upward facing facet facing upwardly and a downward facing facet facing downwardly; forming a second epitaxy semiconductor region on the upward facing facet and the downward facing facet; forming a first metal layer over the second epitaxy semiconductor region on the upward facing facet; and performing a first anneal, wherein the first metal layer reacts with the second epitaxy semiconductor region to form a first metal silicide/germanide layer, the downward facing facet being free of the first metal silicide/germanide layer.

2 . The method of claim 1 , further comprising:
forming a second metal layer over the first metal silicide/germanide layer on the upward facing facet and over the second epitaxy semiconductor region on the downward facing facet; and performing a second anneal, wherein the second metal layer reacts with the first epitaxy semiconductor region to form a second metal silicide/germanide layer, the first metal silicide/germanide layer being a different material than the second metal silicide/germanide layer.

3 . The method of claim 2 , prior to performing the second anneal, forming a nitride layer over the second metal layer on the upward facing facet and the downward facing facet.

4 . The method of claim 3 , wherein the nitride layer is a nitride of a material of the second metal layer.

5 . The method of claim 3 , further comprising forming a contact plug, the contact plug contacting the nitride layer on the upward facing facet and the downward facing facet.

6 . The method of claim 1 , further comprising forming isolation regions on the wafer, the isolation regions being on opposing sides of the first epitaxy semiconductor region, the isolation regions having a concave upper surface.

7 . The method of claim 1 , wherein after performing the first anneal, a portion of the second epitaxy semiconductor region remains on the upward facing facet.

8 . A method comprising:
growing a first epitaxy semiconductor region on a wafer, wherein the first epitaxy semiconductor region comprises an upward facing facet facing upwardly and a downward facing facet facing downwardly; forming a second epitaxy semiconductor region on the upward facing facet and the downward facing facet; forming a first metal silicide/germanide layer over the upward facing facet; and forming a second metal silicide/germanide layer on the downward facing facet, wherein the first metal silicide/germanide layer and the second metal silicide/germanide layer comprise different metals.

9 . The method of claim 8 , wherein forming the first metal silicide/germanide layer comprises:
forming a first metal layer over the second epitaxy semiconductor region on the upward facing facet, the downward facing facet being free of the first metal layer; annealing to cause the first metal layer to react with the second epitaxy semiconductor region; and removing unreacted portions of the first metal layer.

10 . The method of claim 9 , wherein the first metal silicide/germanide layer comprises:
a first germanide sublayer; and a first silicon germanide sublayer.

11 . The method of claim 10 , wherein forming the second metal silicide/germanide layer comprises:
forming a second metal layer over the first metal silicide/germanide layer on the upward facing facet and over the second epitaxy semiconductor region on the downward facing facet; forming a nitride layer over the second metal layer on the upward facing facet and on the downward facing facet; and annealing to cause the second metal layer to react with the second epitaxy semiconductor region on the downward facing facet.

12 . The method of claim 11 , wherein the nitride layer is a nitride of the second metal layer.

13 . The method of claim 12 , wherein the second metal layer and the nitride layer extends over an isolation region adjacent the first epitaxy semiconductor region to an adjacent first epitaxy region.

14 . The method of claim 13 , forming a contact plug, the contact plug contacting the nitride layer over the isolation region.

15 . The method of claim 8 , wherein a portion of the first epitaxy semiconductor region remains unreacted after forming the first metal silicide/germanide layer.

16 . A method comprising:
growing a first epitaxy semiconductor region at a major surface of a wafer, wherein the first epitaxy semiconductor region comprises an upward facing facet facing upwardly and a downward facing facet facing downwardly, and wherein the upward facing facet and the downward facing facet are neither parallel nor perpendicular to the major surface of the wafer; forming a second epitaxy semiconductor region on the upward facing facet and the downward facing facet; forming a first metal layer contacting the second epitaxy semiconductor region; performing a first annealing, wherein the first metal layer reacts with the second epitaxy semiconductor region to form a first metal silicide/germanide layer; forming a second metal layer contacting the second epitaxy semiconductor region on the downward facing facet, wherein the first metal layer and the second metal layer comprise different metals; and performing a second annealing, wherein the second metal layer reacts with the second epitaxy semiconductor region to form a second metal silicide/germanide layer.

17 . The method of claim 16 , wherein forming the second metal layer comprises:
forming a first metal sub-layer over the upward facing facet and the downward facing facet; and forming a first metal nitride sub-layer over the first metal sub-layer.

18 . The method of claim 16 , further comprising removing unreacted portions of the first metal layer after performing the first annealing.

19 . The method of claim 16 , wherein a portion of the second epitaxy semiconductor region remains after the second annealing.

20 . The method of claim 16 , wherein after forming the first metal layer and prior to performing the first annealing, the downward facing facet is free of the first metal layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Chun Hsiung
• Shih Chi-Yuan
• Huang Gin-Chen
• Wann Clement Hsingjen
• Yu Li-Chi
• Lin Chin-Hsiang
• Yeh Ling-Yen
• Chang Meng-Chun
• Chen Neng-Kuo
• Sun Sey-Ping
• Ma Ta-Chun
• Huang Yen-Chun

Classifications

• H10D64/0112 Primary

  using conductive layers comprising silicides · CPC title

• H10P14/20

  of semiconductor materials · CPC title

• H10P10/00 Primary

  Bonding of wafers, substrates or parts of devices · CPC title

• H01L29/0649

  Electricity · mapped topic

• H01L29/45

  Electricity · mapped topic