Access processor

Patent metadata

Field	Value
Publication number	US-2017139629-A1
Application number	US-201514941837-A
Country	US
Kind code	A1
Filing date	Nov 16, 2015
Priority date	Nov 16, 2015
Publication date	May 18, 2017
Grant date	—

Abstract

A reconfigurable computing device having a plurality of reconfigurable partitions and that is adapted to perform parallel processing of operand data by the partitions is provided. The computing system includes a memory device that is adapted to store configuration data to configure the partitions of the computing device, to store operand data to be processed by the configured partitions and to store processing results of the operand data. A programmable memory access processor having a predefined program is provided. The access processor performs address generation, address mapping and access scheduling for retrieving the configuration data from the memory unit, for retrieving the operand data from the memory unit and for storing the processing results in the memory unit. The access processor also transfers the configuration data from the memory unit to the computing device and transfers the operand data from the memory unit to the computing device.

First claim

What is claimed is:

1 . A computing system comprising:
at least one reconfigurable computing device, the reconfigurable computing device having a plurality of reconfigurable partitions and being adapted to perform parallel processing of operand data by the partitions; a memory unit adapted to:
store configuration data to configure the partitions of the reconfigurable computing device;
store operand data to be processed by the configured partitions;
store processing results of the operand data;
a programmable memory access processor comprising a predefined program, the access processor being adapted to:
perform address generation, address mapping and access scheduling for:
retrieving the configuration data from the memory unit;
retrieving the operand data from the memory unit; and
storing the processing results in the memory unit;
transfer the configuration data from the memory unit to the reconfigurable computing device; and
transfer the operand data from the memory unit to the reconfigurable computing device.

2 . A computing system according to claim 1 , wherein the reconfigurable computing device is a field programmable gate array (FPGA).

3 . A computing system according to claim 1 , wherein the memory unit comprises a plurality of memory banks and wherein the access processor is adapted to map the configuration data and/or the operand data over multiple banks.

4 . A computing system according to claim 1 , wherein the access processor is adapted to control the memory access bandwidth assigned to the retrieval of the configuration data and the operand data according to a predefined scheme.

5 . A computing system according to claim 4 , wherein the predefined scheme is one of: a round robin scheme and a priority setting scheme.

6 . A computing system according to claim 1 , wherein the access processor is provided with a preset configuration time required for configuring a partition for a processing operation and wherein the access processor is adapted to schedule the transfer of the operand data for the processing operation in accordance with the preset configuration time.

7 . A computing system according to claim 6 , wherein the access processor is adapted to perform a predefined set of configuration operations and/or processing operations according to predefined parameters.

8 . A computing system according to claim 1 , the computing system comprising a cache memory, the access processor being adapted to store a preselected set of configuration data in the cache memory to facilitate an accelerated configuration of a partition with the preselected configuration data.

9 . A computing system according to claim 1 , the access processor adapted to:
preprocess configuration data stored in the memory unit; and configure a partition of the reconfigurable computing device with the preprocessed configuration data.

10 . A computing system according to claim 1 , wherein the access processor is adapted to provide a broadcast function, the first broadcast function being provided for transferring the same configuration data simultaneously to multiple partitions.

11 . A computing system according to claim 1 , wherein the access processor is adapted to:
store a map of the configured partitions of the reconfigurable computing device; check, upon receipt of operand data for a processing task, whether a partition is already configured for the processing task; transfer the operand data to the respective partition, if a partition is already configured for the processing task; configure a new partition for the processing task, if no partition is already configured for the processing task.

12 . A computing system according to claim 1 , wherein the access processor is adapted to:
configure a plurality of partitions for a common processing task; control the operation of the common processing task in a distributed fashion.

13 . A computing system according to claim 1 , further comprising at least one host processor, communicatively coupled with the access processor, wherein the access processor is adapted to:
receive configuration data comprising a configuration data identifier from the host processor; receive operand data comprising an operand data identifier from the host processor, the operand data identifier indicating a processing task to be performed on the operand data.

14 . A computing system according to claim 1 , wherein the computing system comprises a 3-dimensional chip stack having a plurality of vertical layers, the vertical layers comprising:
a plurality of memory layers comprising the memory unit; a logic layer comprising the access processor; and a computing layer comprising the reconfigurable computing device.

15 . A computing system according to claim 14 , wherein the vertical layers are coupled via Through Silicon Vias (TSVs) and wherein the access processor is adapted to retrieve and transfer the operand data and the configuration data via the TSVs.

16 . A computing system according to claim 14 , wherein the 3-dimensional chip stack comprises a plurality of vertical columns of memory partitions (vaults), wherein each vault further comprises an access processor in the logic layer and a computing device in the computing layer.

17 . A computer implemented method for operating a computing system, the computing system comprising at least one reconfigurable computing device with a plurality of reconfigurable partitions, a memory unit and a programmable memory access processor, the method comprising:
storing, by the memory unit, configuration data to configure the partitions of the reconfigurable computing device; storing, by the memory unit, operand data to be processed by the configured partitions; storing, by the memory unit, processing results of the operand data; performing, by the programmable memory access processor, address generation, address mapping and access scheduling according to a predefined program for: retrieving the configuration data from the memory unit; retrieving the operand data from the memory unit; and storing the processing results in the memory unit; transferring, by the programmable memory access processor, the configuration data from the memory unit to the reconfigurable computing device; and transferring, by the programmable memory access processor, the operand data from the memory unit to the reconfigurable computing device.

18 . A computer implemented method according to claim 17 , the method comprising:
mapping, by the access processor, the configuration data and/or the operand data over multiple banks of the memory unit.

19 . A computer implemented method according to claim 17 , the method comprising:
controlling, by the access processor, the memory access bandwidth assigned to the configuration data and the operand data according to a predefined scheme.

20 . A computer program product for operating a programmable memory access processor of a computing system, the computing system comprising at least one reconfigurable computing device with a plurality of reconfigurable partitions, a memory unit and the programmable memory access processor, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by the access processor to cause the access processor to perform a method comprising:
performing address generation, address mapping and access scheduling according to the program instructions for:
retrieving

Assignees

• IBM

Inventors

• Van Lunteren Jan

Classifications

• G06F2212/60

  Details of cache memory · CPC title

• G06F3/0629 Primary

  Configuration or reconfiguration of storage systems · CPC title

• G06F3/0673

  Single storage device · CPC title

• G11C5/02

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title

• G06F12/0802

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title