Instruction and logic to prefetch information from a persistent memory

Patent metadata

Field	Value
Publication number	US-2017123796-A1
Application number	US-201514926336-A
Country	US
Kind code	A1
Filing date	Oct 29, 2015
Priority date	Oct 29, 2015
Publication date	May 4, 2017
Grant date	—

Abstract

In one embodiment, a processor includes a core having a fetch logic to fetch instructions, a decode logic to decode a first persistent memory prefetch instruction and provide the decoded first persistent memory prefetch instruction to a control logic. In turn, the control logic is to enable prefetch of data requested by the first persistent memory prefetch instruction and storage of the data in a location external to the processor. Other embodiments are described and claimed.

First claim

What is claimed is:

1 . A processor comprising:
a core including a fetch logic to fetch instructions, a decode logic to decode a first persistent memory prefetch instruction and provide the decoded first persistent memory prefetch instruction to a control logic, the control logic to enable prefetch of data requested by the first persistent memory prefetch instruction and storage of the data in a location external to the processor.

2 . The processor of claim 1 , wherein the control logic, responsive to the first persistent memory prefetch instruction, is to prevent storage of the data in the processor.

3 . The processor of claim 2 , wherein the control logic, responsive to a demand request for the data, is to obtain the data from the location external to the processor.

4 . The processor of claim 1 , wherein the location external to the processor comprises a system memory coupled to the processor.

5 . The processor of claim 4 , wherein the system memory comprises a cache memory for the persistent memory, the system memory to be exposed to an application as the cache memory for the persistent memory.

6 . The processor of claim 1 , wherein the location external to the processor comprises a prefetch cache memory of the persistent memory.

7 . The processor of claim 1 , wherein the processor further comprises a memory controller comprising the control logic, the memory controller to discard the first persistent memory prefetch instruction without the prefetch of the data when a memory load is greater than a first threshold.

8 . The processor of claim 7 , wherein the memory controller, responsive to a second persistent memory prefetch instruction, is to enable prefetch of second data and storage of the second data in at least one core of a cache memory of the persistent memory and a system memory coupled to the processor.

9 . A machine-readable medium having stored thereon data, which if performed by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method comprising:
receiving, in a controller of a persistent memory, a first persistent memory prefetch request for first data, the first persistent memory prefetch request issued by an application executing on a processor coupled to the persistent memory; obtaining the first data from a persistent storage of the persistent memory; and storing the first data in a cache memory external to the processor, and not storing the first data in the processor responsive to the first persistent memory prefetch request.

10 . The machine-readable medium of claim 9 , wherein the method further comprises receiving the first persistent memory prefetch request in the controller of the persistent memory via a network connection that couples the processor to the persistent memory.

11 . The machine-readable medium of claim 9 , wherein the cache memory comprises a prefetch cache of the persistent memory.

12 . The machine-readable medium of claim 9 , wherein the method further comprises sending the first data to a memory controller of the processor, to enable the memory controller to send the first data to a second cache memory external to the processor.

13 . The machine-readable medium of claim 9 , wherein the method further comprises sending the first data to a second cache memory external to the processor, responsive to the first persistent memory prefetch request.

14 . The machine-readable medium of claim 9 , wherein the method further comprises sending the first data from the cache memory to the processor responsive to a demand request for the first data, the cache memory comprising a prefetch cache of the persistent memory.

15 . The machine-readable medium of claim 9 , wherein the method further comprises sending the first data from the cache memory to the processor and to a second cache memory external to the processor responsive to a demand request for the first data.

16 . A system comprising:
a processor comprising a core including a fetch logic to fetch instructions, a decode logic to decode a persistent memory prefetch instruction that references a first address in a persistent memory, and a memory controller including a control logic, responsive to the decoded persistent memory prefetch instruction, to cause a prefetch of information stored at the first address and storage of the information in a selected location external to the processor; the persistent memory external to the processor; and a first cache memory external to the processor, the first cache memory formed of volatile memory, and wherein the first cache memory is to cache at least some information stored in the persistent memory.

17 . The system of claim 16 , wherein the persistent memory comprises a prefetch cache, and responsive to a first encoding of the persistent memory prefetch instruction, the control logic is to cause the information to be stored only in the prefetch cache.

18 . The system of claim 17 , wherein responsive to a second encoding of the persistent memory prefetch instruction, the control logic is to cause the information to be stored only in the first cache memory.

19 . The system of claim 16 , wherein the memory controller is to discard the persistent memory prefetch instruction without the prefetch of the information when a load is greater than a first threshold.

20 . The system of claim 16 , wherein the persistent memory comprises a prefetch logic to receive the decoded persistent memory prefetch instruction, obtain the information from a persistent storage of the persistent memory, and store the information in the first cache memory.

Assignees

• Intel Corp

Inventors

• Kumar Karthik
• Dimitrov Martin P

Classifications

• G06F2212/214

  Solid state disk · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F9/30047 Primary

  Prefetch instructions; cache control instructions · CPC title

• G06F9/383

  Operand prefetching (cache prefetching G06F12/0862) · CPC title

• G06F2212/6028

  Prefetching based on hints or prefetch instructions · CPC title