Compilation of application into multiple instruction sets for a heterogeneous processor

Patent metadata

Field	Value
Publication number	US-2017123775-A1
Application number	US-201415128427-A
Country	US
Kind code	A1
Filing date	Mar 26, 2014
Priority date	Mar 26, 2014
Publication date	May 4, 2017
Grant date	—

Abstract

Techniques generally described are related to a method to compile code for a heterogeneous multi-core processor that includes a first core and a second core. The method may include receiving, by a multi-core compilation system, a set of source code that includes a plurality of code segments, wherein the multi-core compilation system is configured to compile the set of source code and generate an executable program that is executable by the heterogeneous multi-core processor. The method may include generating, by the multi-core compilation system, a first instruction set based on a specific code segment selected from the plurality of code segments, wherein the first instruction set is executable by the first core of the heterogeneous multi-core processor. The method may further include, in response to a determination that a performance indicator associated with the first core executing the first instruction set is above a particular threshold, generating, by the multi-core compilation system, a second instruction set based on the specific code segment, wherein the second instruction set is executable by the second core of the heterogeneous multi-core processor, and the first instruction set and the second instruction set are implemented in the executable program.

First claim

1 . A method to compile code for a heterogeneous multi-core processor that includes a first core and a second core, the method comprising:
receiving, by a multi-core compilation system, a set of source code that includes a plurality of code segments, wherein the multi-core compilation system is configured to compile the set of source code and generate an executable program that is executable by the heterogeneous multi-core processor; generating, by the multi-core compilation system, a first instruction set based on a specific code segment selected from the plurality of code segments, wherein the first instruction set is executable by the first core of the heterogeneous multi-core processor; and in response to a determination that a performance indicator associated with the first core executing the first instruction set is above a particular threshold, generating, by the multi-core compilation system, a second instruction set based on the specific code segment, wherein the second instruction set is executable by the second core of the heterogeneous multi-core processor, and the first instruction set and the second instruction set are implemented in the executable program.

2 . The method of claim 1 , further comprising:
generating, by the multi-core compilation system, a condition instruction set for the executable program, wherein the condition instruction set is configured to determine the performance indicator associated with the first core executing the first instruction set during execution of the executable program.

3 . The method of claim 2 , further comprising:
during execution of the executable program, executing, by the multi-core compilation system, the condition instruction set to determine the performance indicator for the first core executing the first instruction set; and in response to a determination that the performance indicator associated with the first core is below the particular threshold, executing, by the multi-core compilation system, the first instruction set using the first core.

4 . The method of claim 3 , further comprising:
in response to the determination that the performance indicator associated with the first core is above the particular threshold, executing, by the multi-core compilation system, the second instruction set using the second core.

5 . The method of claim 1 , further comprising:
generating a scheduling chart for the plurality of code segments; and identifying the specific code segment in the plurality of code segments as having an occurrence count in the scheduling chat that is above a particular occurrence threshold.

6 . The method of claim 1 , wherein the determination of the performance indicator comprises:
collecting a power consumption value of the first core as the performance indicator associated with the first core during execution of the first instruction set.

7 . The method of claim 1 , wherein the determination of the performance indicator comprises:
collecting a temperature value of the first core as the performance indicator associated with the first core during execution of the first instruction set.

8 . A method to compile code for a heterogeneous multi-core processor that includes a first core and a second core, the method comprising:
receiving, by a multi-core compilation system, a set of source code that includes a plurality of code segments, wherein the multi-core compilation system is configured to compile the set of source code into an executable program that is executable by the heterogeneous multi-core processor; generating, by the multi-core compilation system based on the plurality of code segments, a first plurality of instruction sets that are executable by the first core of the heterogeneous multi-core processor; generating, by the multi-core compilation system based on the plurality of code segments, a second plurality of instruction sets that are executable by the second core of the heterogeneous multi-core processor; for a first code segment selected from the plurality of code segments and associated with a first instruction set of the first plurality of instruction sets and a second instruct set of the second plurality of instruction sets, determining, by the multi-core compilation system, a first performance indicator associated with the first core executing the first instruction set and a second performance indicator associated with the second core executing the second instruction set; and in response to a determination that the first performance indicator is above the second performance indicator, selecting, by the multi-core compilation system, the second instruction set to implement the first code segment in the executable program.

9 . The method of claim 8 , wherein the determining the first performance indicator and the second performance indicator comprises:
constructing a regression model by simulating the first core executing the first instruction set; and estimating the first performance indicator associated with the first core based on the regression model and the first instruction set.

10 . The method of claim 8 , further comprising:
determining an execution path having a set of code segments selected from the plurality of code segments, wherein the execution path has an execution frequency in the set of source code that is above a particular frequency threshold; and selecting the first code segment from the set of code segments.

11 . The method of claim 8 , further comprising:
for a second code segment selected from the plurality of code segments and associated with a third instruction set of the first plurality of instruction sets and a fourth instruction set of the second plurality of instruction sets, determining a third performance indicator associated with the first core executing the first instruction set and the third instruction set and a fourth performance indicator associated with the second core executing the second instruction set and the fourth instruction set; and in response to a determination that the third performance indicator is below the fourth performance indicator, selecting the first instruction set and the third instruction set to implement the first code segment and the second code segment in the executable program.

12 . A multi-core compilation system to compile code for a heterogeneous multi-core processor that includes a first core and a second core, the system comprising:
a compiler module configured to:
receive a set of source code that includes a plurality of code segments,
generate a first instruction set for a first code segment selected from the plurality of code segments, wherein the first instruction set is executable by the first core, and
generate a second instruction set for the first code segment, wherein the second instruction set is executable by the second core; and
a code optimization module coupled with the compiler module, wherein the code optimization module is configured to:
link the first instruction set and the second instruction set into an executable program that is executable by the heterogeneous multi-core processor.

13 . The system as recited in claim 12 , further comprising:
an execution module coupled with the code optimization module to execute the executable program, wherein the execution module is configured to:
determine a performance indicator associated with the first core executing the first instruction set, and
in response to the determination that the performance indicator is above a particular threshold, execute the second instruction set using the second core.

14 . The system as recited in claim 13 , wherein the execution m

Assignees

• Empire Technology Dev Llc

Inventors

• Xu Shijie
• Guo Qi
• Li Qi
• Song Xuefeng

Classifications

• G06F8/451 Primary

  Code distribution (considering CPU load at run-time G06F9/505; load rebalancing G06F9/5083) · CPC title