Data transfer techniques for multiple devices on a shared bus

Patent metadata

Field	Value
Publication number	US-2017123715-A1
Application number	US-201514928988-A
Country	US
Kind code	A1
Filing date	Oct 30, 2015
Priority date	Oct 30, 2015
Publication date	May 4, 2017
Grant date	—

Abstract

Direct data transfer between devices having a shared bus may be implemented with reduced involvement from a controller associated with the devices. A controller, a source memory device, and a target memory device may be coupled with a shared bus. The controller may identify a source address at the source memory device for data to be transferred to the target memory device. The controller also may identify a target address in the target memory device, and initiate a data transfer directly from the source to the target through a command that is received at both the source and the target memory device. In response to the command, the source memory device may read data out to the bus, and the target memory may read the data from the bus and store the data starting at the target address without further commands from the controller.

First claim

What is claimed is:

1 . A method of operating a memory system, comprising:
identifying, at a memory controller, a source address in a source memory for data to be transferred to a target memory, wherein the memory controller, the source memory and the target memory are each coupled with a bus; and sending, by the memory controller, a target address to the target memory to initiate a transfer of the data directly from the source memory to the target memory via the bus.

2 . The method of claim 1 , further comprising:
sending a read command to the source memory to read data out of the source memory to the bus.

3 . The method of claim 2 , further comprising:
transferring, by the source memory, data starting at the source address to the bus.

4 . The method of claim 3 , wherein the read command is sent to the source memory via the bus, and wherein the method further comprises:
receiving, by the target memory via the bus, the read command; and storing, in the target memory starting at the target address, subsequent data provided to the bus from the source memory.

5 . The method of claim 4 , wherein the read command comprises a data output instruction and the source address, and wherein receiving the read command by the target memory comprises:
identifying the read command as initiating the transfer of data; and ignoring the source address.

6 . The method of claim 2 , wherein sending the read command further comprises:
providing a chip enable signal to each of the source memory and the target memory; and providing a clock to the source memory and the target memory for a time duration.

7 . The method of claim 6 , wherein the time duration corresponds to an amount of data to be transferred from the source memory to the target memory.

8 . The method of claim 1 , wherein the bus comprises a serial peripheral interconnect (SPI) bus.

9 . The method of claim 1 , wherein the source memory comprises one of a non-volatile memory or a volatile memory and the target memory comprises one of a non-volatile memory or a volatile memory.

10 . A method of operating a memory system, comprising:
setting a target address in a target memory for storage of data to be received at the target memory via a bus that is coupled with the target memory and a source memory; and sending a command to each of the source memory and the target memory to read data out of the source memory to the bus and store the data from the bus at the target memory.

11 . The method of claim 10 , wherein setting the target address comprises:
providing the target address to a target address register of the target memory.

12 . The method of claim 11 , further comprising:
receiving, at an operation instruction decoder of the target memory, the command; and initiating, at the target memory, storage of the data from the bus following the command, starting at the target address.

13 . The method of claim 12 , further comprising:
transferring, by the source memory, data starting at a source address to the bus; and storing, by the target memory, the data from the bus.

14 . The method of claim 10 , wherein the command comprises a single command sequence that is received at each of the source memory and the target memory.

15 . The method of claim 10 , further comprising:
providing a chip enable signal to each of the source memory and the target memory; and providing a clock to the source memory and the target memory for a time duration.

16 . The method of claim 15 , wherein the time duration corresponds to an amount of data to be transferred from the source memory to the target memory.

17 . The method of claim 10 , wherein the bus comprises a serial peripheral interconnect (SPI) bus.

18 . The method of claim 10 , wherein the source memory comprises one of a non-volatile memory or a volatile memory and the target memory comprises one of a non-volatile memory or a volatile memory.

19 . An apparatus for data transfer, comprising:
a first electronic device coupled with a bus, the first electronic device comprising a first data storage area; a second electronic device coupled with the bus, the second electronic device comprising a second data storage area; and a controller coupled with the bus and in electronic communication with the first electronic device and the second electronic device, wherein the controller is operable to:
identify a source address in the first data storage area for data to be transferred from the first data storage area to the second data storage area,
identify a target address in the second data storage area, and
initiate a transfer of the data directly from the first electronic device to the second electronic device via the bus.

20 . The apparatus of claim 19 , wherein the second electronic device comprises a target address register, and wherein the controller is further operable to set the target address in the target address register for storage of the data to be transferred.

21 . The apparatus of claim 19 , wherein the second electronic device comprises an operation instruction decoder that is operable to receive a read command from the controller to initiate the transfer of the data.

22 . The apparatus of claim 19 , wherein the controller comprises a single interface with the bus to access each of the first electronic device and the second electronic device.

23 . The apparatus of claim 19 , wherein the controller is further operable to:
provide a chip enable signal to each of the first electronic device and the second electronic device; and provide a clock to each of the first electronic device and the second electronic device for a time duration that corresponds to an amount of data to be transferred from the first data storage area to the second data storage area.

24 . The apparatus of claim 19 , wherein the first electronic device comprises one of a non-volatile memory or a volatile memory and the second electronic device comprises one of a non-volatile memory or a volatile memory.

25 . An electronic memory apparatus, comprising:
a source memory module coupled with a bus; a target memory module coupled with the bus; and a controller coupled with the bus and in electronic communication with the source memory module and the target memory module, wherein the controller is operable to:
set a target address in the target memory module for storage of data to be received at the target memory module via the bus, and
send a read command to the source memory module to read data out of the source memory module to the bus, and
wherein the target memory module is operable to receive the data read out of the source memory module directly via the bus.

26 . The apparatus of claim 25 , wherein the target memory module comprises a target address register, and wherein the controller is further operable to set the target address in the target address register for storage of the data to be transferred.

27 . The apparatus of claim 26 , wherein the target memory module further comprises an operation instruction decoder that is operable to receive the read command from the controller.

28 . The apparatus of claim 25 , wherein the controller is further operable to:
provide a chip enable signal to each of the source memory module and the target memory module; and provide a clock to each of the source memory modul

Assignees

• Micron Technology Inc

Inventors

• Zhang Yihua
• Cooke James

Classifications

• G06F13/38

  Information transfer, e.g. on bus (G06F13/14 takes precedence) · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F13/4068

  Electrical coupling · CPC title