Low latency scheduling on simultaneous multi-threading cores

Patent metadata

Field	Value
Publication number	US-2017116039-A1
Application number	US-201615051865-A
Country	US
Kind code	A1
Filing date	Feb 24, 2016
Priority date	Oct 22, 2015
Publication date	Apr 27, 2017
Grant date	—

Abstract

A method is provided for prioritized hardware thread scheduling. The method includes, responsive to identifying a latency sensitive workload, enabling, by an operating system, one or more hardware threads to meet dispatch latency demands for the latency sensitive workload. The method further includes responsive to detecting an absence of the latency sensitive workload, de-committing, by the operating system, the one or more hardware threads.

First claim

What is claimed is:

1 . A method for prioritized hardware thread scheduling, the method comprising:
responsive to identifying a latency sensitive workload, enabling, by an operating system, one or more hardware threads to meet dispatch latency demands for the latency sensitive workload; and responsive to detecting an absence of the latency sensitive workload, de-committing, by the operating system, the one or more hardware threads.

2 . The method of claim 1 , wherein the one or more hardware threads are simultaneous multi-threading threads.

3 . The method of claim 1 , further comprising dynamically adjusting, by the operating system, a number of the one or more hardware threads enabled to run low latency threads based on must-complete latency times and workload demands.

4 . The method of claim 3 , further comprising preventing, by the operating system, usage of the one or more hardware threads for hypervisor virtual partition switching.

5 . The method of claim 4 , further comprising masking, by the operating system, input/output interrupts on the one or more hardware threads.

6 . The method of claim 1 , further comprising processing, by a processor core, at least a portion of the latency sensitive workload using the one or more hardware threads.

7 . The method of claim 6 , wherein the processor core is a simultaneous multi-threading processing core.

8 . The method of claim 1 , further comprising:
maintaining, by the operating system, at least one of the one or more hardware threads as at least one idle hardware thread, further responsive to detecting the absence of the latency sensitive workload, wherein the at least one idle hardware thread only looks for other latency sensitive workloads in a local run queue associated with the at least one idle hardware thread.

9 . The method of claim 1 , wherein the latency sensitive workload is identified responsive to a request for low-latency scheduling for the latency sensitive workload.

10 . The method of claim 1 , wherein the method is performed in a simultaneous multi-threading computing environment.

11 . The method of claim 1 , wherein at least one of the one or more hardware threads manages a plurality of software threads relating to the latency sensitive workload.

Assignees

• IBM

Inventors

• Mealey Bruce
• Warrier Suresh E

Classifications

• G06F2009/4557

  Distribution of virtual machine instances; Migration and load balancing · CPC title

• G06F9/45533

  Hypervisors; Virtual machine monitors · CPC title

• G06F9/4881 Primary

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/5044

  considering hardware capabilities · CPC title

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title