Techniques for limiting power via secondary control of a voltage regulator

Patent metadata

Field	Value
Publication number	US-2017102760-A1
Application number	US-201514879040-A
Country	US
Kind code	A1
Filing date	Oct 8, 2015
Priority date	Oct 8, 2015
Publication date	Apr 13, 2017
Grant date	—

Abstract

A power subsystem is configured to manage the maximum power usage of a computer subsystem. A power detector determines when power usage approaches the maximum capability of the power supply. The power detector generates a signal that corresponds to power usage. A controller then applies the signal to the system voltage regulator as a secondary regulation function such that the output voltage is reduced in a manner that supports maximum operating voltage while limiting power usage to within the capability of the power supply. The controller may configure the signal to implement the secondary regulation function as a modification of the feedback voltage, the reference voltage, or the current feedback of the regulator. As a result the subsystem causes the computer subsystem to operate at an optimum point on the voltage-current curve of the power supply.

First claim

The invention claimed is:

1 . A subsystem configured to regulate power to a processor, the subsystem comprising:
a voltage regulator configured to output a first voltage, wherein the first voltage has a maximum power capability; a power detector configured to generate a first signal that represents an amount of power being used by the processor; and a controller configured to:
determine that the amount of power being used by the processor is approaching the maximum power capability,
combine the first signal with a control signal to generate a second signal, wherein the control signal represents a modification to the first voltage, and
transmit the second signal to the voltage regulator, causing the voltage regulator to reduce the first voltage thus limiting the amount of power being used by the processor.

2 . The subsystem of claim 1 , wherein the power detector is further configured to:
receive a third signal that represents a current input to the regulator; receive a fourth signal that represents an amount of current being used by the processor; compare a magnitude of the third signal and a magnitude of the fourth signal; and generate the first signal that represents the amount of power being used by the processor based on a difference between the magnitude of the third signal and the magnitude of the fourth signal.

3 . The subsystem of claim 2 , wherein the controller is further configured to:
receive the first signal; receive the control signal that represents the first voltage; generate the second signal based on a sum of the first signal and the control signal; and transmitting the second signal to the voltage feedback input of the voltage regulator.

4 . The subsystem of claim 2 , wherein the controller is further configured to:
receive the first signal; receive the control signal that represents a reference voltage; generate the second signal based on a difference between the first signal and the control signal; and transmit the second signal to the reference input of the voltage regulator.

5 . The subsystem of claim 1 , further configured to:
receive a fifth signal that represents a current output of the regulator; compare the fifth signal to a threshold level; and generate the first signal that represents the amount of power being used by the processor based on the current output of the regulator.

6 . The subsystem of claim 5 , wherein the controller is further configured to:
receive the first signal; receive the control signal that represents the first voltage; generate the second signal based on a sum of the first signal and the control signal; and transmit the second signal to the voltage feedback input of the voltage regulator.

7 . The subsystem of claim 5 , wherein the controller is further configured to:
receive the first signal; receive the control signal that represents a reference voltage; generate the second signal based on a difference between the first signal and the control signal; and transmit the second signal to the reference input of the voltage regulator.

8 . The subsystem of claim 1 , further configured to:
receive a fifth signal that represents a current output of the regulator; receive a sixth signal that represents a current computed by the processor; compute a seventh signal based on the fifth signal and the sixth signal; compare the seventh signal to a threshold level; and generate the first signal that represents the amount of power being used by the processor.

9 . The subsystem of claim 8 , wherein the controller is further configured to:
receive the first signal; receive the control signal that represents the first voltage; generate the second signal based on a sum of the first signal and the control signal; and transmit the second signal to the voltage feedback input of the voltage regulator.

10 . The subsystem of claim 8 , wherein the controller is further configured to:
receive the first signal; receive the control signal that represents a reference voltage; generate the second signal based on a difference between the first signal and the control signal; and transmit the second signal to the reference input of the voltage regulator.

11 . The subsystem of claim 8 , wherein the controller is further configured to transmit the first signal to a current input of the regulator.

12 . A computer-implemented method for regulating power to a processor, the method comprising:
receiving a first voltage that is output to the processor, wherein the first voltage has a maximum power capability; determining that an amount of power being used by the processor is approaching the maximum power capability; generating a first signal that represents the amount of power being used by the processor; combining the first signal with a control signal to generate a second signal, wherein the control signal represents a modification to the first voltage; and transmitting the second signal to a regulator that causes the regulator to reduce the first voltage to limit the amount of power being used by the processor.

13 . The computer-implemented method of claim 12 , wherein determining that the amount of power being used by the processor is approaching the maximum power capability comprises:
receiving a third signal that represents a current input to the regulator; receiving a fourth signal that represents an amount of current being used by the processor; comparing a magnitude of the third signal and a magnitude of the fourth signal; and computing the amount of power being used by the processor based on a difference between the magnitude of the third signal and the magnitude of the fourth signal.

14 . The computer-implemented method of claim 12 , wherein determining that the amount of power being used by the processor is approaching the maximum power capability comprises:
receiving a fifth signal that represents a current output of the regulator; and comparing the fifth signal to a threshold level.

15 . The computer-implemented method of claim 14 wherein transmitting the second signal to the regulator comprises transmitting the second signal to a current input of the regulator.

16 . The computer-implemented method of claim 12 wherein generating the second signal comprises computing a sum of the first signal and the first voltage.

17 . The computer-implemented method of claim 12 wherein generating the second signal comprises computing a difference between the first signal and a reference voltage.

18 . The computer-implemented method of claim 12 wherein the second signal causes the regulator to decrease the first voltage linearly without exceeding the maximum power capability.

19 . The computer-implemented method of claim 12 wherein the regulator is configured to reduce the voltage by:
decreasing the first voltage by an incremental amount;
determining that amount of power being used by the processor is still approaching the maximum power capability; and
decreasing the first voltage linearly without exceeding the maximum power capability.

20 . A computing device, comprising:
a processor; a voltage regulator configured to output a first voltage, wherein the first voltage has a maximum power capability; a power detector configured to generate a first signal that represents the amount of power being used by the processor; and a controller configured to:
combine the first signal with a control signal to generate a second signal, wherein the control signal represents a

Assignees

• Nvidia Corp

Inventors

• Duell Sam
• Alben Jonah
• Bell Andrew R
• Chen Ming
• Gorla Gabriele
• Lin Qi
• Pang Henry
• SANTHIRAKUMARAN Gokul

Classifications

• G06F1/3296 Primary

  by lowering the supply or operating voltage · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title