Watchdog scheme for monitoring a power electronic inverter and determining a manner of operating a load

Patent metadata

Field	Value
Publication number	US-2017102437-A1
Application number	US-201514878290-A
Country	US
Kind code	A1
Filing date	Oct 8, 2015
Priority date	Oct 8, 2015
Publication date	Apr 13, 2017
Grant date	—

Abstract

In one example embodiment, a circuit includes a first sub-circuit configured to generate first data corresponding to a frequency and a duration of overloading of a transistor in the inverter, and a second sub-circuit configured to generate second data corresponding to a rate of rise of a voltage and a peak voltage value of the transistor in the inverter. The first sub-circuit and the second sub-circuit are configured to respectively provide the first data and second data as outputs to a controller for analyzing a manner in which a load coupled to the inverter is driven.

First claim

What is claimed is:

1 . A circuit comprising:
a first sub-circuit configured to generate first data corresponding to a frequency and a duration of overloading of a transistor in the inverter; and a second sub-circuit configured to generate second data corresponding to a rate of rise of a voltage and a peak voltage value of the transistor in the inverter; wherein the first sub-circuit and the second sub-circuit are configured to respectively provide the first data and second data as outputs to a controller for analyzing a manner in which a load coupled to the inverter is driven.

2 . The circuit of claim 1 , wherein the first sub-circuit is configured to generate the first data during a turn-off event of the transistor.

3 . The circuit of claim 2 , wherein the turn-off event takes place when the transistor supplies peak current or near-peak current to the load.

4 . The circuit of claim 2 , wherein the first data is a series of pulses.

5 . The circuit of claim 1 , wherein the second sub-circuit is configured to generate the second data during the turn-off event of the transistor.

6 . The circuit of claim 7 , wherein the second sub-circuit is configured to generate the second data by measuring a voltage across a resistor in the second sub-circuit.

7 . The circuit of claim 1 , wherein the controller is configured to analyze the manner in which the load is driven by,
receiving the first data, and determining the frequency and the duration of overloading the transistor based on frequencies and widths of pulses included in the first data.

8 . The circuit of claim 7 , wherein the controller is further configured to analyze the manner in which the load is driven by,
receiving the second data, determining, based on the second data, a temperature of the transistor during the turn-off event, developing a degradation model for the transistor based on the determined temperature, and determining a schedule for performing a maintenance of the transistor based on the degradation model and a maintenance look-up table.

9 . The circuit of claim 1 , further comprising:
a third sub-circuit coupled to the first and second sub-circuits, the third sub-circuit being configured to operate as an over-voltage protection for the transistor.

10 . The circuit of claim 1 , wherein the transistor is one of an Insulated-Gate Bipolar Transistor (IGBT), a metal-oxide Semiconductor Field-Effect Transistor (MOSFET), a Silicon Carbide MOSFET or a Silicon Carbide IGBT.

11 . A system comprising:
a plurality of transistors forming an inverter; and a plurality of circuits, each of the plurality of circuits being coupled to one of the plurality of transistors, each of the plurality of circuitries being configured to monitor the corresponding one of the plurality of transistors by,
generating first data corresponding to a frequency and a duration of overloading of the corresponding one of the plurality of transistors, and
generating second data corresponding to a rate of rise of a voltage and a peak voltage value of the corresponding one of the plurality of transistors, wherein
each of the plurality of circuits is configured to provide the corresponding first data and the second data as outputs to a controller for analyzing a manner in which a load coupled to the inverter is driven.

12 . The system of claim 11 , wherein each of the plurality of transistors comprises:
a first sub-circuit configured to generate the first data during a turn-off event of the corresponding one of the plurality of transistors; and a second sub-circuit configured to generate the second data during the turn-off event of the corresponding one of the plurality of transistors.

13 . The system of claim 12 , wherein the turn-off event takes place when the corresponding one of the plurality of transistors supplies peak current or near-peak current to the load.

14 . The system of claim 12 , wherein the first data is a series of pulses.

15 . The system of claim 12 , wherein the second sub-circuit is configured to generate the second data by measuring a voltage across a resistor in the second sub-circuit.

16 . The system of claim 12 , wherein each of the plurality of transistors further comprises:
a third sub-circuit coupled to the first and second sub-circuits, the third sub-circuit being configured to operate as an over-voltage protection for the corresponding one of the plurality of transistors.

17 . The system of claim 11 , wherein the controller is configured to analyze the manner in which the load is driven by,
receiving the first data and the second data, and analyzing, based on the first data and the second data, the manner in which the load is driven.

18 . The system of claim 17 , wherein the controller is configured to analyze the manner in which the load is driven by determining the frequency and the duration of overloading the transistors based on a frequency and width of pulses included in the first data.

19 . The system of claim 17 , wherein the controller is configured to analyze the manner in which the load is driven by,
determining, based on the second data, a temperature of the corresponding one of the plurality of transistors during the turn-off event, developing a degradation model for the corresponding one of the plurality of transistors based on the determined temperature, and determining a schedule for performing a maintenance of the corresponding one of the plurality of transistors based on the degradation model and a maintenance look-up table.

20 . The system of claim 11 , wherein each of the plurality of transistors is one of an Insulated-Gate Bipolar Transistor (IGBT), a metal-oxide Semiconductor Field-Effect Transistor (MOSFET), a Silicon Carbide MOSFET or a Silicon Carbide IGBT.

Assignees

• Deere & Co

Inventors

• Singh Brij N
• Clements Neal D
• Desai Advait

Classifications

• H02P29/68

  based on the temperature of a drive component or a semiconductor component · CPC title

• H02H7/122

  for inverters, i.e. DC/AC converters · CPC title

• G01R31/42 Primary

  AC power supplies · CPC title

• H02M7/53875

  with analogue control of three-phase output · CPC title

• H03K17/18

  Modifications for indicating state of switch · CPC title