Non-volatile storage for graphics hardware

US2017091981A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2017091981-A1
Application numberUS-201615335670-A
CountryUS
Kind codeA1
Filing dateOct 27, 2016
Priority dateMay 29, 2010
Publication dateMar 30, 2017
Grant date

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  1. Title

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Methods and systems may provide for an apparatus having a graphics processing unit (GPU) and a non-volatile memory dedicated to the GPU. If a request for content is detected, a determination may be made as to whether the non-volatile memory contains the content.

First claim

Opening claim text (preview).

1 . (canceled) 2 . A graphics card comprising: a graphics processing unit (GPU) on the graphics card; a volatile memory on the graphics card, the volatile memory dedicated to the GPU; an interface on the graphics card to enable communication with a solid state drive (SSD); a bridge chip on the graphics card to enable communication between the GPU and the interface on the graphics card via a peripheral components interconnect express (PCIe) bus on the graphics card, wherein the PCIe bus on the graphics card is to enable GPU control of the SSD; and wherein the GPU is to access the SSD for data when the data is not stored in the volatile memory on the graphics card. 3 . The graphics card as in claim 2 , wherein the GPU is to request the data from a CPU when the data is not stored on the SSD. 4 . The graphics card as in claim 3 , wherein the GPU, via the PCIe bus on the graphics card, is to instruct the SSD to perform a read operation, the read operation to supply a bus address of an exposed portion of the volatile memory on the graphics card. 5 . The graphics card as in claim 4 , wherein the volatile memory on the graphics card is to receive output of the read operation via the PCIe bus on the graphics card. 6 . The graphics card as in claim 5 , wherein the SSD is accessible to the GPU as local memory. 7 . The graphics card as in claim 2 , wherein the GPU is to request a unit of data via a host PCIe interface when the unit of data is not found on the SSD. 8 . The graphics card as in claim 7 , the volatile memory on the graphics card to receive the unit of data via the host PCIe interface. 9 . The graphics card as in claim 8 , the GPU to persistently store the unit of data to the SSD via the PCIe bus on the graphics card, wherein the PCIe bus on the graphics card is dedicated to the GPU. 10 . The graphics card as in claim 2 , wherein the volatile memory on the graphics card is graphics double data rate (GDDR) memory. 11 . The graphics card as in claim 10 , wherein the GPU is to directly control the SSD via the PCIe bus on the graphics card. 12 . A data processing system comprising: a host processor including one or more cores; a display controller device; a display device to display output of the display controller device; a graphics card coupled to the host processor via a host peripheral components interconnect express (PCIe) interface, the graphics card including: a graphics processing unit (GPU) on the graphics card; volatile memory on the graphics card, the volatile memory dedicated to the GPU; an interface on the graphics card to enable a connection to a solid state drive (SSD); and a bridge chip to couple the GPU to the interface on the graphics card via a PCIe bus on the graphics card, the PCIe bus to enable GPU control of the SSD, wherein the GPU is to access the SSD for data via the PCIe bus on the graphics card when the data is not in the volatile memory on the graphics card. 13 . The data processing system as in claim 12 , wherein the GPU is to request the data from the host processor when the data is not stored on the SSD. 14 . The data processing system as in claim 13 , wherein the GPU, via the PCIe bus on the graphics card, is to instruct the SSD to perform a read operation, the read operation to supply a bus address of an exposed portion of the volatile memory on the graphics card. 15 . The data processing system as in claim 14 , wherein the volatile memory on the graphics card is to receive output of the read operation via the PCIe bus on the graphics card. 16 . The data processing system as in claim 15 , wherein the SSD is accessible to the GPU as local memory. 17 . The data processing system as in claim 12 , wherein the GPU is to: request a unit of data via the host PCIe interface when the unit of data is not found via the request through the interface on the graphics card; receive the unit of data via the host PCIe interface in response to the request; and persistently store the unit of data via a write to the interface on the graphics card. 18 . The data processing system as in claim 12 , wherein the volatile memory on the graphics card is graphics double data rate (GDDR) memory. 19 . The data processing system as in claim 18 , wherein the GPU is to directly control the SSD via the PCIe bus on the graphics card. 20 . A non-transitory machine readable medium storing instructions to cause one or more processors to perform operations to process data on a graphics card having a graphics processing unit (GPU) connected to a dedicated solid state drive (SSD) via an peripheral components interconnect express (PCIe) bus on the graphics card that is dedicated to the GPU, the operations comprising: receiving a request at the GPU to perform an operation on a unit of data; instructing the SSD to perform a read operation, the read operation supplying a bus address of a volatile memory on the graphics card, wherein the volatile memory is dedicated to the GPU; receiving the unit of data at the volatile memory, the unit of data received from the SSD via the PCIe bus on the graphics card; and processing the unit of data via the GPU. 21 . The non-transitory machine readable medium as in claim 20 , the operations additionally comprising persistently storing the unit of data to the SSD after processing the unit of data, the unit of data stored via a write to the PCIe bus on the graphics card. 22 . The non-transitory machine readable medium as in claim 20 , the operations additionally comprising determining whether the unit of data resides in the volatile memory on the graphics card before reading the unit of data from the SSD. 23 . The non-transitory machine readable medium as in claim 22 , the operations additionally comprising requesting the unit of data from a host processor connected to the graphics card when the unit of data is not stored on the SSD. 24 . The non-transitory machine readable medium as in claim 23 , the operations additionally comprising: receiving the unit of data at the volatile memory, the unit of data received from the host processor via a host PCIe interface; and persistently storing the unit of data to the SSD via the PCIe bus on the graphics card after processing the unit of data via the GPU. 25 . The non-transitory machine readable medium as in claim 20 , the operations additionally comprising directly controlling the SSD via the PCIe bus on the graphics card. 26 . The non-transitory machine readable medium as in claim 25 , the operations additionally comprising configuring the GPU to access the SSD via the PCIe bus on the graphics card.

Assignees

Inventors

Classifications

  • Mixed reality (object pose determination, tracking or camera calibration for mixed reality G06T7/00) · CPC title

  • Memory management · CPC title

  • G06T15/005Primary

    General purpose rendering architectures · CPC title

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Frequently asked questions

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What does patent US2017091981A1 cover?
Methods and systems may provide for an apparatus having a graphics processing unit (GPU) and a non-volatile memory dedicated to the GPU. If a request for content is detected, a determination may be made as to whether the non-volatile memory contains the content.
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification G06T15/005. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Mar 30 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).