Asymmetric source/drain depths

Patent metadata

Field	Value
Publication number	US-2017084498-A1
Application number	US-201615369635-A
Country	US
Kind code	A1
Filing date	Dec 5, 2016
Priority date	Dec 24, 2014
Publication date	Mar 23, 2017
Grant date	—

Abstract

A method for fabricating a semiconductor device includes forming a relaxed semiconductor layer on a substrate, the substrate comprising an n-type region and a p-type region. The method further includes forming a tensile strained semiconductor layer on the relaxed semiconductor layer, etching a portion of the tensile strained semiconductor layer in the p-type region, forming a compressive strained semiconductor layer on the tensile strained semiconductor layer in the p-type region, forming a first gate in the n-type region and a second gate in the p-type region, and forming a first set of source/drain features adjacent to the first gate and a second set of source/drain features adjacent to the second gate. The second set of source/drain features are deeper than the first set of source/drain features.

First claim

What is claimed is:

1 . A method for forming a semiconductor device, the method comprising:
forming a relaxed semiconductor layer on a substrate, the substrate comprising an n-type region and a p-type region; forming a tensile strained semiconductor layer on the relaxed semiconductor layer; forming a compressive strained semiconductor layer on the tensile strained semiconductor layer in the p-type region; forming a first gate in the n-type region and a second gate in the p-type region; and forming a first set of source/drain features adjacent to the first gate and a second set of source/drain features adjacent to the second gate, the second set of source/drain features being deeper than the first set of source/drain features, wherein a channel length between the first set of source/drain features is greater than a channel length between the second set of source/drain features.

2 . The method of claim 1 , further comprising, an isolation structure between the p-type region and the n-type region.

3 . The method of claim 1 , wherein the second set of source/drain features comprise a tip-shaped profile.

4 . The method of claim 3 , wherein the tip-shaped profile is in an upper portion of the second set of source/drain features and a lower portion of the second set of source/drain features comprises a straight profile.

5 . The method of claim 1 , wherein the first set of source/drain features have a rounded profile on a side that faces a channel between the first set of source/drain features.

6 . The method of claim 1 , wherein a lattice constant of the tensile strained semiconductor layer is less than a lattice constant of the relaxed semiconductor layer.

7 . The method of claim 1 , wherein a lattice constant of the compressive strained semiconductor layer is greater than a lattice constant of the relaxed semiconductor layer.

8 . The method of claim 1 , wherein a lattice constant of the first set of source/drain features is less than a lattice constant of the tensile strained semiconductor layer.

9 . The method of claim 1 , wherein a lattice constant of the second set of source/drain features is greater than a lattice constant of the compressive strained semiconductor layer.

10 . The method of claim 1 , wherein the first set of source/drain features and the second set of source/drain features have a higher dopant concentration on top than on bottom.

11 . The method of claim 1 , wherein the first set of source/drain features do not extend to the relaxed semiconductor layer.

12 . The method of claim 1 , wherein the second set of source/drain features extends into the relaxed semiconductor layer.

13 . A method for forming a semiconductor device, the method comprising:
providing a substrate having a first region and a second region; forming an n-type transistor in the first region, the n-type transistor comprising a first set of source/drain features; and forming a p-type transistor in the second region, the p-type transistor comprising a second set of source/drain features; wherein the second set of source/drain features extend deeper than the first set of source/drain features.

14 . The method of claim 13 , wherein the p-type transistor and the n-type transistor are fin Field Effect Transistors (finFETs).

15 . The method of claim 13 , wherein a channel of the n-type transistor comprises a tensile strained material and a channel of the p-type transistor comprises a compressive strained material.

16 . The method of claim 13 , wherein a portion along a bottom of the first set of source/drain features comprises a higher concentration of n-type dopants than a remaining portion of the first set of source/drain features.

17 . The method of claim 13 , wherein a portion along a top of the second set of source/drain features comprises a higher concentration of p-type dopants than a remaining portion of the second set of source/drain features.

18 . A method of fabricating a semiconductor device, the method comprising:
forming a relaxed semiconductor layer on a substrate, the substrate comprising an n-type region and a p-type region; forming a tensile strained semiconductor layer on the relaxed semiconductor layer; etching a portion of the tensile strained semiconductor layer in the p-type region; forming a compressive strained semiconductor layer on the tensile strained semiconductor layer in the p-type region; forming a first gate in the n-type region and a second gate in the p-type region; forming a first set of source/drain features adjacent to the first gate and a second set of source/drain features adjacent to the second gate, the second set of source/drain features being deeper than the first set of source/drain features.

19 . The method of claim 18 , further comprising, forming an isolation structure between the p-type region and the n-type region.

20 . The method of claim 19 , further comprising, after forming the compressive semiconductor layer, etching the isolation structure to form a first fin-like structure in the n-type region and a second fin-like structure in the p-type region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Cheng-Yi
• Yang Yu-Lin
• Ho Chia-Cheng
• Chiu Jung-Piao
• Lee Tsung-Lin
• Chang Chih Chieh
• Yeo Yee-Chia

Classifications

• H10P50/642

  Chemical etching · CPC title

• H01L29/1054

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic

• H01L21/823807

  Electricity · mapped topic