Electromagnetic Interference (EMI) for Pulse Frequency Modulation (PFM) Mode of a Switching Regulator

Patent metadata

Field	Value
Publication number	US-2017070145-A1
Application number	US-201514845381-A
Country	US
Kind code	A1
Filing date	Sep 4, 2015
Priority date	Sep 4, 2015
Publication date	Mar 9, 2017
Grant date	—

Abstract

A circuit and method providing switching regulation configured to provide a pulse frequency modulation (PFM) mode of operation with reduced electromagnetic interference (EMI) comprising an output stage configured to provide switching comprising a first and second transistor, a sense circuit configured to provide output current information sensing from an output stage and a current limit reference, a first digital-to-analog converter (DAC) configured to provide signal to the current limit reference, an adder function configured to provide a signal to the first digital-to-analog converter (DAC), and a linear shift feedback register (LSFR) configured to provide a signal to an adder function followed by the first digital-to-analog converter (DAC), and the LSFR receives a clock signal from said output stage.

First claim

What is claimed is:

1 . A power converter running in a pulse frequency modulation (PFM) mode, comprising:
an output stage configured to provide switching comprising a first and second transistor; a controller configured to switch between said first and second transistors based on a current limit; a sense circuit configured to provide output current information sensing from said output stage and a current limit reference; and a current limit jitter block configured to jitter said current limit and spread an emission spectrum.

2 . The power converter of claim 1 , further comprising:
a linear shift feedback register (LSFR) configured to reduce electromagnetic interference (EMI) emitted by said power converter by spreading the emission spectrum.

3 . The power converter of claim 2 , wherein said linear shift feedback register (LSFR) generates a pseudo-random distribution around a nominal average programmed limit.

4 . The power converter of claim 2 , further comprising:
a first digital-to-analog converter (DAC) configured to provide a signal to the current limit reference; an adder function configured to provide a signal to said first digital-to-analog converter (DAC); and, said linear shift feedback register (LSFR) configured to provide a signal to the adder function and receiving a clock signal from said output stage.

5 . The power converter of claim 1 , providing switching regulation configured to provide a pulse frequency modulation (PFM) mode of operation with reduced electromagnetic interference (EMI).

6 . The power converter of claim 1 , wherein said output stage comprises a p-channel MOS (PMOS) transistor and an n-channel MOS (NMOS) transistor.

7 . The power converter of claim 1 , further comprising a gate driver circuit configured to provide a gate signal to said output stage.

8 . The power converter of claim 7 , further comprising a control logic block to provide switching signals to the gate driver circuit.

9 . The power converter of claim 1 , further comprising an inductor configured to receive a current from said output stage, said power converter configured to provide a feedback signal.

10 . The power converter of claim 4 , further comprising a second digital-to-analog converter (DAC) configured to provide a second DAC voltage.

11 . The power converter of claim 10 , further comprising of a comparator circuit configured to receive a feedback signal and said second DAC voltage and providing an under-voltage output signal.

12 . A circuit with a jitter scheme comprising:
a digital-to-analog converter (DAC) providing a digital to analog voltage signal; a comparator comparing said digital to analog voltage signal to a feedback voltage signal and providing an over-voltage signal and an under-voltage signal; a second digital-to-analog converter (DAC) providing an offset signal to said comparator; a zero-cross block; a jitter block configured to jitter said offset signal and spread an emission spectrum; and a pass devices block is configured to provide a signal to a said zero-cross block.

13 . The circuit of claim 12 , wherein a current limit litter block is provided to add jitter to a current limit.

14 . The circuit of claim 12 , wherein the jitter is added to the offset between the digital-to-analog voltage signal and an upper threshold voltage.

15 . The circuit of claim 14 , wherein each time the pass-devices stop switching, the offset is adjusted to a new value, around the nominal offset value providing a change in a delay before the next burst of switching activity.

16 . The circuit of claim 12 wherein said jitter block comprises:
a Linear Shift Frequency Register (LSFR) block configured to modify a nominal comparator offset value;
an adder receiving a signal from said Linear Shift Frequency Register (LSFR).

17 . The circuit in claim 14 , wherein said comparator is configured to provide said over-voltage signal if said feedback voltage signal is above said upper threshold voltage and said under-voltage signal if said feedback signal is below said digital to analog voltage signal.

18 . A method of providing a reduced electromagnetic interference (EMI) power distribution in a switching regulator in pulse frequency mode (PFM) of operation comprising the steps of:
providing a circuit with an output stage, a sense circuit, a digital-to-analog converter (DAC), an adder, and a functional block; generating a signal from said output stage; clocking said functional block with said signal from said output stage; generating a pseudo-random signal from said functional block; mixing said pseudo-random signal from said functional block with a current limit value by said adder; and providing the adder signal via the digital-to-analog converter (DAC) to a current limit reference for power spectrum distribution.

19 . The method of claim 18 wherein said functional block is a Linear Shift Frequency Register (LSFR) block.

20 . The method of claim 18 , wherein the circuit further comprises:
a feedback loop, a second digital-to-analog converter (DAC), a comparator, a control functional block, gate drivers, and an inductor coil.

21 . The method of claim 20 , further comprising the steps of:
feeding a feedback signal through said feedback loop from said inductor coil; generating a digital-to-analog converter (DAC) voltage signal from said second DAC; comparing said feedback signal and said second DAC voltage signal; generating a under-voltage signal from said comparator; and generating a current limit signal from said sense circuit.

22 . The method of claim 20 , further comprising the steps of:
feeding an under-voltage signal and a current limit signal to said control functional block; applying voltage signals to the gate drivers for switching; feeding switching signals to the output stage; switching said output stage based on the switching signals; and providing the clock signal to the linear switching feedback register (LSFR) from said output stage state.

23 . The method of claim 22 , wherein said output stage comprises of a p-channel MOS (PMOS) transistor, and a n-channel MOS (NMOS) transistor.

24 . A method of providing a reduced electromagnetic interference (EMI) power distribution in a switching regulator in pulse frequency mode (PFM) of operation comprising the steps of:
providing a circuit with an output stage, a sense circuit, a digital-to-analog converter (DAC), an adder, and a linear shift frequency register (LSFR); generating a signal from said output stage; clocking said linear shift register (LSFR) with a said signal from said output stage; generating a pseudo-random signal from said linear shift register (LSFR); adding said pseudo-random signal from said linear shift register (LSFR) with a current limit value by said adder; and providing the adder signal via the digital-to-analog converter (DAC) to a current limit reference for power spectrum distribution.

Assignees

• Dialog Semiconductor Uk Ltd

Inventors

• Childs Mark
• Patrao Tiago
• Gallina Pietro
• Tavares Alexandre
• De Fazio Michele

Classifications

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M1/44 Primary

  Circuits or arrangements for compensating for electromagnetic interference in converters or inverters · CPC title

• H02M3/156

  with automatic control of output voltage or current, e.g. switching regulators · CPC title