Inductor device

Patent metadata

Field	Value
Publication number	US-2017069707-A1
Application number	US-201615340683-A
Country	US
Kind code	A1
Filing date	Nov 1, 2016
Priority date	Jan 26, 2014
Publication date	Mar 9, 2017
Grant date	—

Abstract

A semiconductor device includes an inductor disposed on a surface of an intermetallic dielectric layer at a location below which no virtual interconnect members are present. Thus, parasitic capacitance is reduced or eliminated and the Q value of the inductor is high.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a front-end device; an interlayer dielectric layer on the front-end device, an interconnect member within the interlayer dielectric layer and connected with the front-end device; a dielectric filling layer within the interlayer dielectric layer; an intermetallic dielectric layer on the interlayer dielectric layer; and an inductor on the intermetallic dielectric layer.

2 . The semiconductor device of claim 1 , wherein the inductor has a projection in a direction vertical to the intermetallic dielectric layer covering the dielectric filling layer.

3 . The semiconductor device of claim 1 , wherein the dielectric filler layer and the interlayer dielectric layer are formed of a same material.

4 . The semiconductor device of claim 1 , wherein the front-end device comprises:
a semiconductor substrate; a transistor on and in the semiconductor substrate; a dielectric layer on the semiconductor substrate; an interconnect member disposed within the dielectric layer; and a metal plug within the dielectric layer connected with the interconnect member.

5 . The semiconductor device of claim 1 , further comprising a barrier layer interposed between the interlayer dielectric layer and the intermetallic dielectric layer.

6 . The semiconductor device of claim 5 , wherein the dielectric filling layer is coplanar with an upper surface of the barrier layer.

7 . An electronic apparatus comprising a semiconductor device, the semiconductor device comprises:
a front-end device; an interlayer dielectric layer on the front-end device, an interconnect member within the interlayer dielectric layer and connected with the front-end device; a dielectric filling layer within the interlayer dielectric layer; an intermetallic dielectric layer on the interlayer dielectric layer; and an inductor on the intermetallic dielectric layer.

8 . The electronic apparatus of claim 7 , wherein the inductor has a projection in a direction vertical to the intermetallic dielectric layer covering the dielectric filling layer.

9 . The electronic apparatus of claim 7 , wherein the dielectric filler layer and the interlayer dielectric layer are formed of a same material.

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Huang Herb He
• Ge Hongtao
• Li Haiting

Classifications

• H10P95/064

  the removal being chemical etching · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title