Phase synchronization with low frequency sampling

Patent metadata

Field	Value
Publication number	US-2017063383-A1
Application number	US-201514838204-A
Country	US
Kind code	A1
Filing date	Aug 27, 2015
Priority date	Aug 27, 2015
Publication date	Mar 2, 2017
Grant date	—

Abstract

This disclosure provides a device and method for synchronizing local oscillator (LO) chains. The method can include sampling first I-data and first Q-data to generate first sampled I-data and first sampled Q-data based on a sampling clock signal. The method can also include calibrating the sampling clock signal based on the first sampled I-data and the first sampled Q-data to generate a first calibrated sampling clock signal, the first calibrated sampling clock signal indicating an optimal sample position to sample the first I-data and the first Q-data. The method can also include synchronizing a phase of the first LO chain and a second LO chain based on the first calibrated sampling clock signal.

First claim

What is claimed is:

1 . A method for local oscillator (LO) phase synchronization, the method comprising:
sampling first I-data and first Q-data from an input signal to generate first sampled I-data and first sampled Q-data based on a sampling clock signal; calibrating the sampling clock signal based on the first sampled I-data and the first sampled Q-data to generate a first calibrated sampling clock signal, the first calibrated sampling clock signal indicating an optimal sample position to sample the first I-data and the first Q-data; and synchronizing a phase of a first LO chain and a second LO chain based on the first calibrated sampling clock signal.

2 . The method of claim 1 further comprising:
sampling second I-data and second Q-data from the input signal to generate second sampled I-data and second sampled Q-data based on the sampling clock signal;
calibrating the sampling clock signal based on the second sampled I-data and the second sampled Q-data to generate a second calibrated sampling clock signal; and
synchronizing the phase of the first LO chain and the second LO chain further based on the second calibrated sampling clock signal.

3 . The method of claim 2 further comprising:
dividing the input signal into the first I-data and the first Q-data; and
dividing the input signal into the second I-data and the second Q-data.

4 . The method of claim 2 , wherein the synchronizing comprises flipping a phase of one of the first LO chain and the second LO chain by 180 degrees.

5 . The method of claim 3 further comprising:
dividing the input signal into third I-data and third Q-data for a third LO chain;
calibrating the sampling clock signal using one or more delay increments to determine the optimal sample position of the third I-data and the third Q-data; and
synchronizing the third LO chain with the first LO chain and the second LO chain.

6 . The method of claim 2 further comprising calibrating the sampling clock signal for the first LO chain using a first time delay and calibrating the sampling clock signal for the second LO chain using a second time delay.

7 . The method of claim 2 , wherein the calibrating comprises delaying the sampling clock signal by one or more delay increments for the first LO chain and one or more delay increments for the second LO chain.

8 . The method of claim 7 , wherein the calibrating further comprises saving the one or more delay increments in a memory and comparing values of two or more samples of at least one of the first I-data and the first Q-data taken at the one or more delay increments to indicate the optimal sample position for the first I-data and the first Q-data.

9 . The method of claim 2 , wherein the first I-data and first Q-data for the first LO chain is out of phase with the second I-data and the second Q-data for the second LO chain.

10 . The method of claim 3 , wherein dividing the input signal comprises dividing a frequency of the input signal in half with a divide-by-two LO divider for each of the first LO chain and the second LO chain, the input signal being supplied by a voltage controlled oscillator (VCO).

11 . The method of claim 1 further comprising determining the optimal sample position for the first I-data based on a transition point of the first Q-data, the transition point being a point at which a value of the first Q-data changes between binary values.

12 . The method of claim 1 further comprising determining the optimal sample position for the first Q-data based on a transition point of the first I-data, the transition point being a point at which a value of the first I-data changes between binary values.

13 . The method of claim 1 , wherein the calibrating comprises sampling the first I-data and the first Q-data based on the sampling clock signal without adding any delay increments.

14 . A device for local oscillator (LO) phase synchronization, the device comprising:
a plurality of samplers configured to sample first I-data and first Q-data for a first LO chain to generate first sampled I-data and first sampled Q-data based on a sampling clock signal; and a controller operably coupled the plurality of samplers, the controller being configured to
calibrate the sampling clock signal based on the first sampled I-data and the first sampled Q-data to generate a first calibrated sampling clock signal, the first calibrated sampling clock signal indicating an optimal sample position of the first I-data and the first Q-data, and
synchronize a phase of the first LO chain and a second LO chain based on the first calibrated sampling clock signal.

15 . The device of claim 14 further comprising:
a plurality of samplers configured to sample second I-data and second Q-data for the second LO chain to generate second sampled I-data and second sampled Q-data based on a sampling clock signal,
wherein the controller is further configured to:
calibrate the sampling clock signal based on the second sampled I-data and the second sampled Q-data to generate a second calibrated sampling clock signal, the second calibrated sampling clock signal indicating an optimal sampling position to sample the second I-data and the second Q-data; and
synchronize the phase of the first LO chain and the second LO chain further based on the second calibrated sampling clock signal.

16 . The device of claim 15 , wherein the controller is further configured to flip a phase of one of the first LO chain and the second LO chain by 180 degrees.

17 . The device of claim 15 further comprising:
a first LO divider configured to divide an input signal into the first I-data and the first Q-data; and
a second LO divider configured to divide the input signal into the second I-data and the second Q-data.

18 . The device of claim 17 further comprising:
a third LO divider configured to divide the input signal into third I-data and third Q-data for a third LO chain;
wherein the controller is further configured to calibrate the sampling clock signal using one or more delay increments to determine the optimal sample position of the third I-data and the third Q-data; and
synchronize the third LO chain with the first LO chain and the second LO chain.

19 . The device of claim 15 wherein the controller is further configured to calibrate the sampling clock signal for the first LO chain using a first time delay and calibrate the sampling clock signal for the second LO chain using a second time delay.

20 . The device of claim 15 , wherein the controller is further configured to delay the sampling clock signal by one or more delay increments for the first LO chain and one or more delay increments for the second LO chain.

21 . The device of claim 20 further comprising:
a sample clock generator configured to generate the sampling clock signal; and
a plurality of delay buffers coupled to the sample clock generator, each of delay buffer of the plurality of delay buffers configured to output a delayed sampling clock signal with a delay associated with one of the one or more delay increments,
wherein the controller is further configured to select one or more of the delay buffers associated with the one or more delay increments in a memory and compare values of two or more samples of the first I-data and the first Q-data taken at the one or more delay increments to indicate the optimal sample position for the first I-data and the first Q-data.

22 . The device of claim 15 , wherein the first I-dat

Assignees

• Qualcomm Inc

Inventors

• Yang Jeongsik
• Rajavi Yashar
• Johansen Keplin Victor
• Bicakci Ara

Classifications

• H03L7/081 Primary

  provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)} · CPC title

• H04B7/0452

  Multi-user MIMO systems · CPC title

• H03L7/0807

  concerning mainly a recovery circuit for the reference signal · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H04W56/0015 Primary

  one node acting as a reference for the others · CPC title