Semiconductor device and method for forming the same

Patent metadata

Field	Value
Publication number	US-2017062484-A1
Application number	US-201514872156-A
Country	US
Kind code	A1
Filing date	Oct 1, 2015
Priority date	Aug 28, 2015
Publication date	Mar 2, 2017
Grant date	—

Abstract

The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device including a substrate, an oxide semiconductor layer, two source/drain regions, a high-k dielectric layer and a bottom oxide layer. The oxide semiconductor layer is disposed on a first insulating layer disposed on the substrate. The source/drain regions are disposed on the oxide semiconductor layer. The high-k dielectric layer covers the oxide semiconductor layer and the source structure and the drain regions. The bottom oxide layer is disposed between the high-k dielectric layer and the source/drain regions, wherein the bottom oxide layer covers the source/drain regions and the oxide semiconductor layer.

First claim

1 . A semiconductor device, comprising:
a substrate; an oxide semiconductor layer disposed on a first insulating layer disposed on the substrate; two source/drain regions disposed on the oxide semiconductor layer; a high-k dielectric layer covering the oxide semiconductor layer and the source/drain regions; a bottom oxide layer between the high-k dielectric layer and the source/drain regions, covering the source/drain regions and the oxide semiconductor layer; and a second insulating layer disposed between the oxide semiconductor layer and the source/drain regions, wherein each source/drain region is vertically aligned with the oxide semiconductor layer and the second insulating layer.

2 . (canceled)

3 . The semiconductor device according to claim 2 , wherein the second insulating layer comprises an oxide semiconductor material different from that of the oxide semiconductor layer.

4 . The semiconductor device according to claim 2 , wherein the second insulating layer has a thickness smaller than that of the oxide semiconductor layer.

5 . The semiconductor device according to claim 2 , wherein the second insulating layer and the oxide semiconductor layer comprise indium gallium zinc oxide (InGaZnO), InGaO 2 , InZnO 2 , GaInO, ZnInO, or GaZnO.

6 - 7 . (canceled)

8 . The semiconductor device according to claim 1 , further comprising:
a second gate electrode disposed below the oxide semiconductor layer and overlapped the oxide semiconductor layer.

9 . The semiconductor device according to claim 8 , further comprising:
a third insulating layer disposed between the oxide semiconductor layer and the second gate electrode, wherein the third insulating layer comprises a oxide semiconductor material different from the oxide semiconductor layer.

10 . The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises a monolayer structure or a multilayer structure.

11 . (canceled)

12 . A method for forming a semiconductor device, comprising:
providing a substrate having a first insulating layer formed thereon; forming an oxide semiconductor layer on the first insulating layer; forming two source/drain regions on the oxide semiconductor layer; forming a bottom oxide layer covering the source/drain regions; forming high-k dielectric layer on the bottom oxide layer; and performing a oxygen treatment on the high-k dielectric layer in the presence of a gas containing an oxygen element.

13 . The method for forming a semiconductor device according to claim 12 , further comprising:
forming a second insulating layer between the oxide semiconductor layer and the source/drain regions, wherein the second insulating layer comprises a oxide semiconductor material different from the oxide semiconductor layer.

14 . The method for forming a semiconductor device according to claim 13 , wherein the second insulating layer and the oxide semiconductor layer comprise indium gallium zinc oxide (InGaZnO), InGaO 2 , InZnO 2 , GaInO, ZnInO, or GaZnO.

15 . The method for forming a semiconductor device according to claim 12 , further comprising:
forming a top oxide layer on the high-k dielectric layer, wherein the bottom oxide layer, the high-k dielectric layer and the top oxide layer consists a sandwiched gate dielectric structure; and forming a first gate electrode between the source/drain regions and on the sandwiched gate dielectric structure, wherein the first gate electrode is vertically aligned with the top oxide layer and the high-k dielectric layer.

16 . The method for forming a semiconductor device according to claim 15 , wherein the forming of the sandwiched gate dielectric structure and the first gate electrode comprises:
sequentially forming a high-k dielectric material layer and an oxide layer covered on the bottom oxide layer; forming a gate layer on the oxide layer; and simultaneously patterning the high-k dielectric material layer, the oxide layer and the gate layer, to form the first gate electrode, the high-k dielectric layer and the top oxide layer.

17 . The method for forming a semiconductor device according to claim 12 , further comprising:
forming a second gate electrode below the oxide semiconductor layer, wherein the second gate electrode overlaps the oxide semiconductor layer.

18 . The method for forming a semiconductor device according to claim 12 , wherein the oxygen treatment is performed by supplying 100% O 2 gas under 400° C.

19 . The method for forming a semiconductor device according to claim 12 , further comprising:
forming a first contact structure electrically connected to the source/drain regions.

20 . The method for forming a semiconductor device according to claim 15 , further comprising:
forming a second contact structure electrically connected to the first gate electrode.

21 . A semiconductor device, comprising:
a substrate; an oxide semiconductor layer disposed on a first insulating layer disposed on the substrate; two source/drain regions disposed on the oxide semiconductor layer; a high-k dielectric layer covering the oxide semiconductor layer and the source/drain regions; a bottom oxide layer between the high-k dielectric layer and the source/drain regions, covering the source/drain regions and the oxide semiconductor layer; a top oxide layer disposed on the high-k dielectric layer, wherein the bottom oxide layer, the high-k dielectric layer and the top oxide layer consists of a sandwiched gate dielectric structure; and a first gate electrode disposed between the two source/drain regions and on the sandwiched gate dielectric structure, wherein the first gate electrode overlaps the oxide semiconductor layer, and the top oxide layer and the high-k dielectric layer are vertically aligned with the first gate electrode.

22 . A semiconductor device, comprising:
a substrate; an oxide semiconductor layer disposed on a first insulating layer disposed on the substrate; two source/drain regions disposed on the oxide semiconductor layer; a high-k dielectric layer covering the oxide semiconductor layer and the source/drain regions; a bottom oxide layer between the high-k dielectric layer and the source/drain regions, covering the source/drain regions and the oxide semiconductor layer; and two via plugs electrically connected to the two source/drain regions respectively, wherein the via plugs do not contact the high-k dielectric layer.

Assignees

• United Microelectronics Corp

Inventors

• Hsu Chia-Fu
• Wu Chun-Yuan

Classifications

• H10P14/6519

  the substance being oxygen · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/60

  of insulating materials · CPC title

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title