Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-2017059909-A1
Application number	US-201615342410-A
Country	US
Kind code	A1
Filing date	Nov 3, 2016
Priority date	Oct 30, 2009
Publication date	Mar 2, 2017
Grant date	—

Abstract

When a pixel portion and a driver circuit are formed over one substrate and a counter electrode is formed over an entire surface of a counter substrate, the driver circuit may be adversely affected by an optimized voltage of the counter electrode. A semiconductor device according to the present invention has a structure in which: a liquid crystal layer is provided between a pair of substrates; one of the substrates is provided with a pixel electrode and a driver circuit; the other of the substrates is a counter substrate which is provided with two counter electrode layers in different potentials; and one of the counter electrode layers overlaps with the pixel electrode with the liquid crystal layer therebetween and the other of the counter electrode layers overlaps with the driver circuit with the liquid crystal layer therebetween. An oxide semiconductor layer is used for the driver circuit.

First claim

1 . (canceled)

2 . A semiconductor device comprising:
a first electrode layer and a second electrode layer over a first substrate; a liquid crystal layer over the first electrode layer and the second electrode layer; a first counter electrode layer and a second counter electrode layer over the liquid crystal layer; a second substrate over the first counter electrode layer and the second counter electrode layer; and a transistor in a driver circuit, the transistor comprising:
a channel formation region including an oxide semiconductor, the channel formation region comprising a first region; and
a source region including the oxide semiconductor, the source region comprising a second region,
wherein a concentration of oxygen in the first region is higher than a concentration of oxygen in the second region, wherein the first electrode layer is a pixel electrode formed in a position overlapping with the first counter electrode layer with the liquid crystal layer therebetween, and wherein the second electrode layer is an electrode layer of the driver circuit formed in a position overlapping with the second counter electrode layer with the liquid crystal layer therebetween.

3 . The semiconductor device according to claim 2 , wherein a potential of the first counter electrode layer is different from a potential of the second counter electrode layer.

4 . The semiconductor device according to claim 2 , wherein the first electrode layer is electrically connected to a thin film transistor in a pixel portion.

5 . The semiconductor device according to claim 2 , wherein the second electrode layer is a gate electrode layer of a thin film transistor of the driver circuit.

6 . The semiconductor device according to claim 2 further comprising:
a third electrode layer over the first substrate; and
a conductive particle between the third electrode layer and the first counter electrode layer,
wherein the third electrode layer is electrically connected to the first counter electrode layer through the conductive particle.

7 . The semiconductor device according to claim 2 further comprising:
a fourth electrode layer over the first substrate; and
a conductive particle between the fourth electrode layer and the second counter electrode layer,
wherein the fourth electrode layer is electrically connected to the second counter electrode layer through the conductive particle.

8 . A semiconductor device comprising:
a first electrode layer, a second electrode layer, a third electrode layer, and a fourth electrode layer over a first substrate; a liquid crystal layer over the first electrode layer and the second electrode layer; a first counter electrode layer and a second counter electrode layer over the liquid crystal layer; a second substrate over the first counter electrode layer and the second counter electrode layer; and a transistor in a driver circuit, the transistor comprising:
a channel formation region including an oxide semiconductor, the channel formation region comprising a first region; and
a source region including the oxide semiconductor, the source region comprising a second region,
wherein a concentration of oxygen in the first region is higher than a concentration of oxygen in the second region, wherein the third electrode layer is electrically connected to the first counter electrode layer through a first conductive particle, wherein the fourth electrode layer is electrically connected to the first counter electrode layer through a second conductive particle, wherein the first electrode layer is a pixel electrode formed in a position overlapping with the first counter electrode layer with the liquid crystal layer therebetween, and wherein the second electrode layer is an electrode layer of the driver circuit formed in a position overlapping with the second counter electrode layer with the liquid crystal layer therebetween.

9 . The semiconductor device according to claim 8 , wherein a potential of the first counter electrode layer is different from a potential of the second counter electrode layer.

10 . The semiconductor device according to claim 8 , wherein the first electrode layer is electrically connected to a thin film transistor in a pixel portion.

11 . The semiconductor device according to claim 8 , wherein the second electrode layer is a gate electrode layer of a thin film transistor of the driver circuit.

12 . The semiconductor device according to claim 8 further comprising:
a fifth electrode layer over the first substrate; and
a third conductive particle between the fourth electrode layer and the second counter electrode layer,
wherein the fifth electrode layer is electrically connected to the second counter electrode layer through the third conductive particle.

Assignees

• Semiconductor Energy Lab

Inventors

• Koyama Jun
• Yamazaki Shunpei

Classifications

• G02F1/133784

  by rubbing · CPC title

• G02F1/1339

  Gaskets; Spacers; Sealing of cells · CPC title

• G02F1/13394

  spacers regularly patterned on the cell subtrate, e.g. walls, pillars (G02F1/133377 takes precedence) · CPC title

• G02F1/137

  characterised by the electro-optical or magneto-optical effect, e.g. field-induced phase transition, orientation effect, guest-host interaction or dynamic scattering · CPC title

• G02F1/13454

  Drivers integrated on the active matrix substrate (G02F1/136277 takes precedence) · CPC title