Optimizing power in a memory device

Patent metadata

Field	Value
Publication number	US-2017052584-A1
Application number	US-201615248364-A
Country	US
Kind code	A1
Filing date	Aug 26, 2016
Priority date	Jun 12, 2012
Publication date	Feb 23, 2017
Grant date	—

Abstract

Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

First claim

1 . (canceled)

2 . A memory device comprising:
a first circuit to receive an external clock signal and generate a reduced clock signal, such that, during a given interval, a number of pulses of the reduced clock is less than a number of pulses of the external clock signal; a delay-locked loop (DLL) circuit to receive the reduced clock signal as an input and generate a second clock signal based on the reduced clock signal; a first latency counter clocked by the reduced clock signal; and a second latency counter clocked by the second clock signal, wherein the first and second latency counters to indicate a time for outputting data from the memory device relative to a received read command.

3 . The memory device of claim 2 , further comprising:
an input buffer to receive the read command and to receive a first mode command from a memory controller, the first mode command to cause the memory device to enter an idle mode.

4 . The memory device of claim 3 , wherein responsive to the memory device entering the idle mode, the second latency counter to receive one or more edges of the second clock signal after the first latency counter stops counting.

5 . The memory device of claim 3 , wherein the input buffer to further receive a second mode command from the memory controller, the second mode command to cause the memory device to exit the idle mode.

6 . The memory device of claim 5 , wherein responsive to the memory device exiting the idle mode, the first latency counter to receive one or more edges of the reduced clock signal before the second latency counter starts counting.

7 . The memory device of claim 2 , wherein the DLL circuit to delay the second clock signal with respect to the reduced clock signal to synchronize the first latency counter and the second latency counter when the memory device exits an idle mode.

8 . The memory device of claim 2 , wherein the reduced clock signal comprises no more than two pulses selected from at least three consecutive pulses of the external clock signal during the given interval.

9 . A method of operation in a memory device, the method comprising:
receiving, by a first circuit, an external clock signal and generating a reduced clock signal, such that, during a given interval, a number of pulses of the reduced clock is less than a number of pulses of the external clock signal; receiving, by a delay-locked loop (DLL) circuit, the reduced clock signal as an input and generating a second clock signal based on the reduced clock signal; clocking a first latency counter by the reduced clock signal; and clocking a second latency counter by the second clock signal, wherein the first and second latency counters to indicate a time for outputting data from the memory device relative to a received read command.

10 . The method of claim 9 , further comprising:
receiving, by an input buffer, the read command and a first mode command from a memory controller, the first mode command to cause the memory device to enter an idle mode.

11 . The method of claim 10 , further comprising:
responsive to the memory device entering the idle mode, receiving, by the second latency counter, one or more edges of the second clock signal after the first latency counter stops counting.

12 . The method of claim 10 , further comprising:
receiving, by the input buffer, a second mode command from the memory controller, the second mode command to cause the memory device to exit the idle mode.

13 . The method of claim 12 , further comprising:
responsive to the memory device exiting the idle mode, receiving, by the first latency counter, one or more edges of the reduced clock signal before the second latency counter starts counting.

14 . The method of claim 9 , further comprising:
delaying, by the DLL circuit, the second clock signal with respect to the reduced clock signal to synchronize the first latency counter and the second latency counter when the memory device exits an idle mode.

15 . The method of claim 9 ,
wherein the reduced clock signal comprises no more than two pulses selected from at least three consecutive pulses of the external clock signal during the given interval.

16 . A system comprising:
a memory controller; and a memory device coupled to the memory controller, the memory device comprising:
a first circuit to receive an external clock signal and generate a reduced clock signal, such that, during a given interval, a number of pulses of the reduced clock is less than a number of pulses of the external clock signal;
a delay-locked loop (DLL) circuit to receive the reduced clock signal as an input and generate a second clock signal based on the reduced clock signal;
a first latency counter clocked by the reduced clock signal; and
a second latency counter clocked by the second clock signal, wherein the first and second latency counters to indicate a time for outputting data from the memory device relative to a received read command.

17 . The system of claim 16 , wherein the memory device further comprises:
an input buffer to receive the read command and to receive a first mode command and a second mode command from the memory controller, the first mode command to cause the memory device to enter an idle mode and the second mode command to cause the memory device to exit the idle mode.

18 . The system of claim 17 , wherein responsive to the memory device entering the idle mode, the second latency counter to receive one or more edges of the second clock signal after the first latency counter stops counting.

19 . The system of claim 17 , wherein responsive to the memory device exiting the idle mode, the first latency counter to receive one or more edges of the reduced clock signal before the second latency counter starts counting.

20 . The system of claim 17 , wherein the DLL circuit to delay the second clock signal with respect to the reduced clock signal to synchronize the first latency counter and the second latency counter when the memory device exits the idle state.

21 . The system of claim 16 , wherein the reduced clock signal comprises no more than two clock pulses selected from at least three consecutive pulses of the external clock signal during the given interval.

Assignees

• Rambus Inc

Inventors

• Patil Dinesh
• Amirkhany Amir
• Aquil Farrukh
• Kaviani Kambiz
• Ware Frederick A

Classifications

• G11C7/1057 Primary

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G06F2205/067

  Bidirectional FIFO, i.e. system allowing data transfer in two directions · CPC title

• G06F5/065

  Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's · CPC title