Mitigation of latency disparity in a transaction processing system

Patent metadata

Field	Value
Publication number	US-2017046783-A1
Application number	US-201614991654-A
Country	US
Kind code	A1
Filing date	Jan 8, 2016
Priority date	Aug 12, 2015
Publication date	Feb 16, 2017
Grant date	—

Abstract

Systems and methods are disclosed which match or otherwise allocate an incoming transaction with previously received but not yet fully satisfied transactions counter thereto as well as to mitigation of disparities in latencies between the client devices of the market participants and the electronic data transaction processing system which may result in disparities in the time of receipt of competing transactions. The disclosed embodiments may mitigate such disparities by buffering or otherwise grouping temporally proximate competing transactions together upon receipt, e.g. into a group, collection, set, bucket, etc., and subsequently arbitrating among those grouped competing transactions, in a manner other than solely based on the order in which the competing transactions in the group were received, to determine the order in which those competing transactions will be processed, thereby equalizing priority of transactions received from participants having varying abilities to rapidly submit transactions or otherwise capitalize on transactional opportunities.

First claim

What is claimed is:

1 . A system for mitigating latency disparity between different client devices and an electronic data transaction processing system in which data items are transacted by a hardware matching processor that matches, as they are received, incoming electronic data transaction request messages, for one of the data items based on a first set of transaction parameters, received from the different client devices over a data communication network with at least one other previously received but unsatisfied electronic data transaction request message counter thereto to at least partially satisfy one or both of the incoming electronic data transaction request messages or the at least one other previously received electronic data transaction request message, wherein the first set of transaction parameters comprises a first parameter having a first value, and further wherein each of the incoming electronic data transaction request messages may include a second parameter having a second value, the system comprising:
first logic stored in a first memory and executable by a first processor coupled therewith to cause the first processor to determine an occurrence of a first event and a subsequent occurrence of a second event; second logic stored in the first memory and executable by the first processor to cause, upon determination of occurrence of the first event, the first processor to receive incoming electronic data transaction request messages and store the received incoming electronic data transaction request messages in a second memory coupled with the first processor prior to forwarding the received incoming electronic data transaction request messages to the hardware matching processor; third logic stored in the first memory and executable by the first processor to cause the first processor to, upon the occurrence of the second event, identify a first subset of at least two of the stored incoming electronic data transaction request messages wherein values of at least a subset of the first set of transaction parameters thereof are identical, and determine whether the hardware matching processor would match any of the first subset of stored incoming electronic data transaction request messages, based on the first set of transaction parameters thereof, with at least one other previously received but unsatisfied electronic data transaction request message counter thereto to at least partially satisfy one or both of the stored incoming electronic data transaction request messages or the at least one other previously received electronic data transaction request message; fourth logic stored in the first memory and executable by the first processor to cause the first processor to, upon the occurrence of the second event, based on the first set of transaction parameters thereof, with at least one other previously received but unsatisfied electronic data transaction request message counter thereto to at least partially satisfy one or both of the stored incoming electronic data transaction request messages or the at least one other previously received electronic data transaction request message, modify the first value of the first transaction parameter of the first set of transaction parameters of each of the stored incoming electronic data transaction request messages based on the second value of the second parameter, if included therewith, and determine based on the modified first set of transaction parameters of each of the stored incoming electronic data transaction request messages, at least one second subset thereof which would be matched by the hardware matching processor with at least one other previously received but unsatisfied electronic data transaction request message counter thereto to at least partially satisfy one or both of the second subset of stored incoming electronic data transaction request messages or the at least one other previously received electronic data transaction request message, and forward each stored electronic data transaction request message of each of the at least one second subset, each having, if modified, the modified first set of transaction parameters, to the hardware matching processor in the order in which they were received by the first processor and, subsequent thereto, forward each remaining stored electronic data transaction request message of the first subset, each having their associated first set of transaction parameters, to the hardware matching processor in the order in which they were received by the first processor.

2 . The system of claim 1 wherein the incoming electronic data transaction request messages may include a request to modify at least one other previously received electronic data transaction request message, the system further comprising:
fifth logic stored in the first memory and executable by the first processor to cause the first processor to, upon the occurrence of the second event and wherein it is determined that the hardware matching processor would match any of the first subset of stored incoming electronic data transaction request messages, based on the first set of transaction parameters thereof, with at least one other previously received but unsatisfied electronic data transaction request message counter thereto to at least partially satisfy one or both of the stored incoming electronic data transaction request messages or the at least one other previously received electronic data transaction request message, identify and forward to the hardware matching processor any of the stored incoming electronic data transaction request messages comprising a request to modify any of at least one other previously received but unsatisfied electronic data transaction request messages to the extent those identified stored incoming electronic data transaction request messages comprising a request to modify any of at least one other previously received but unsatisfied electronic data transaction request messages would have been effective if at least all of the subset of stored incoming electronic data transaction request messages and the identified stored incoming electronic data transaction request messages comprising a request to modify any of at least one other previously received but unsatisfied electronic data transaction request messages were forwarded to the hardware matching processor in the order in which they were received by the first processor;
wherein the fourth logic is further executable by the processor upon the occurrence of the second event and subsequent to the forwarding of any of the stored incoming electronic data transaction request messages comprising a request to modify any of at least one other previously received but unsatisfied electronic data transaction request messages, and wherein it is subsequently determined that the hardware matching processor would still match any of the first subset of stored incoming electronic data transaction request messages.

3 . A system for mitigating latency disparity between different client devices and an electronic data transaction processing system in which data items are transacted by a hardware matching processor that matches, as they are received, incoming electronic data transaction request messages, for one of the data items based on a first set of transaction parameters, received from the different client devices over a data communication network with at least one other previously received but unsatisfied electronic data transaction request message counter thereto to at least partially satisfy one or both of the incoming electronic data transaction request messages or the at least one other previously received electronic data transaction request message, wherein the first set of transaction parameters comprises a first parameter having a first value, and further wherein each of the incoming electronic data transaction request messages may incl

Assignees

• Chicago Mercantile Exchange Inc

Inventors

• Hosman Bernard
• Castette Sean
• Malabre Fred
• Peck-Walden Pearce
• Studnitzer Ari

Classifications

• G06Q40/04 Primary

  Trading; Exchange, e.g. stocks, commodities, derivatives or currency exchange · CPC title

• G06Q40/06

  Asset management; Financial planning or analysis · CPC title

• H04L67/42

  Electricity · mapped topic