Workload balancing in multi-core video decoder

Patent metadata

Field	Value
Publication number	US-2017034522-A1
Application number	US-201614992008-A
Country	US
Kind code	A1
Filing date	Jan 10, 2016
Priority date	Jul 29, 2015
Publication date	Feb 2, 2017
Grant date	—

Abstract

A multi-core decoder for decoding compressed video picture data decodes compressed video picture data. Multi-core processing resources parse compressed video picture data, and decode structures of picture data stored in a temporary storage. A control module adapts the resources of the cores by allocating at least one core to parse picture data serially, and allocating other cores to decode picture data in parallel. The multi-core processing resources are allocated between parsing and decoding picture data as a function of a workload parameter related to the relative workloads of the parsing and decoding operations.

First claim

1 . A multi-core video decoder for decoding compressed video picture data, the decoder comprising:
multi-core processing resources including a plurality of cores that perform parsing operations in parallel with decoding operations on picture data to be decoded; and a control module that allocates a selected number of the cores to serial data parsing operations of a respective picture, and allocates other cores to parallel picture data decoding operations.

2 . The multi-core video decoder of claim 1 , wherein the control module adapts the resources of the cores as a function of a workload parameter related to the relative workloads of the parsing and decoding operations.

3 . The multi-core video decoder of claim 2 , wherein the workload parameter for current picture data is related to relative durations of parsing operations and of decoding operations for preceding picture data.

4 . The multi-core video decoder of claim 3 , wherein the workload parameter is related to the relative values of a duration of parsing operations for preceding picture data that is a function of a difference between end and start times of the parsing operations on a core, and of a duration of decoding operations that is a function of decoding times of samples of picture elements for the preceding picture data and of a sample rate.

5 . The multi-core video decoder of claim 4 , wherein the duration of decoding operations is a function of the decoding times of the samples of picture elements after deduction of waiting times.

6 . The multi-core video decoder of claim 3 , wherein the workload parameter is a time difference between a completion time of decoding operations and a completion time of parsing operations for corresponding preceding picture data relative to a threshold value.

7 . The multi-core video decoder of claim 6 , wherein the control module allocates unchanged numbers of the cores to the parsing and decoding operations as long as the parsing operations for current picture data are completed in time for prompt decoding operations for the same picture data.

8 . The multi-core video decoder of claim 2 , wherein the control module allocates respective numbers of the cores to the parsing and decoding operations as a function of the workload parameter.

9 . The multi-core video decoder of claim 1 , wherein the control module allocates a plurality of the cores to the serial parsing operations of data of respective pictures, wherein the decoder includes temporary storage for storing the results of the parsing operations, and wherein the control module allocates at least one other of the cores to decoding data of at least one picture using the stored parsing results.

10 . The multi-core video decoder of claim 1 , wherein the control module allocates the cores repeatedly as a function of at least one of (i) periodically, (ii) detection of a change of bit rate of the picture data to be decoded, and (iii) a change in the number of the number of cores available for parsing and decoding operations.

11 . A multi-core video decoder for decoding compressed video picture data, the decoder comprising:
multi-core processing resources including a plurality of cores that perform parsing and decoding operations on picture data to be decoded; and a control module that allocates the cores between operations of parsing picture data and decoding picture data as a function of a workload parameter related to relative workloads of the parsing and decoding operations.

12 . The multi-core video decoder of claim 11 , wherein the control module allocates cores to serially parse data of respective pictures, and allocates other cores to decode picture data in parallel.

13 . The multi-core video decoder of claim 11 , wherein the workload parameter for current picture data is related to relative durations of parsing operations and of decoding operations for preceding picture data.

14 . The multi-core video decoder of claim 13 , wherein the workload parameter is related to the relative values of a duration of parsing operations for preceding picture data that is a function of a difference between end and start times of the parsing operations on a core, and of a duration of decoding operations that is a function of decoding times of samples of picture elements for the preceding picture data and of a sample rate.

15 . The multi-core video decoder of claim 14 , wherein the duration of decoding operations is a function of the decoding times of the samples of picture elements after deduction of waiting times.

16 . The multi-core video decoder of claim 13 , wherein the workload parameter is a time difference between a completion time of decoding operations and a completion time of parsing operations for corresponding preceding picture data relative to a threshold value.

17 . The multi-core video decoder of claim 16 , wherein the control module allocates unchanged numbers to the parsing and decoding operations as long as the parsing operations for current picture data are completed in time for prompt decoding operations for the same picture data.

18 . The multi-core video decoder of claim 11 , wherein the control module allocates respective numbers of the cores to the parsing and decoding operations, and adapts the numbers as a function of the workload parameter.

19 . The multi-core video decoder of claim 11 , wherein the control module allocates a plurality of the cores to the serial parsing operations of data of respective pictures, wherein the decoder includes temporary storage for storing the results of the parsing operations, and wherein the control module allocates at least one other of the cores to decoding data of at least one picture using the stored parsing results.

20 . The multi-core video decoder of claim 11 , wherein the control module adapts the resources of the cores repeatedly as a function of at least one of (i) periodically, (ii) detection of a change of bit rate of the picture data to be decoded, and (iii) a change in the number of the number of cores available for parsing and decoding operations.

Assignees

• Freescale Semiconductor Inc

Inventors

• Yang Hongzhang
• Huang Chaofan
• Zhou Peng

Classifications

• G06F9/5011

  the resources being hardware resources other than CPUs, Servers and Terminals · CPC title

• H04N19/436 Primary

  using parallelised computational arrangements · CPC title

• H04N19/44

  Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder · CPC title

• G06F9/505

  considering the load · CPC title