Intelligent code apparatus, method, and computer program for memory

Patent metadata

Field	Value
Publication number	US-2017031762-A1
Application number	US-201514811763-A
Country	US
Kind code	A1
Filing date	Jul 28, 2015
Priority date	Jul 28, 2015
Publication date	Feb 2, 2017
Grant date	—

Abstract

An intelligent code apparatus, method, and computer program are provided for use with memory. In operation, a subset of data stored in a first memory is identified. Such subset of the data stored in the first memory is processed, to generate a code. The code is then stored in a second memory, for use in reconstructing at least a portion of the data.

First claim

What is claimed is:

1 . An apparatus, comprising:
a first memory for storing data; a second memory; and circuitry in communication with the first memory and second memory, the circuitry configured for:
identifying a subset of the data stored in the first memory,
processing the subset of the data stored in the first memory, to generate a code, and
storing the code in the second memory, for use in reconstructing at least a portion of the data.

2 . The apparatus of claim 1 , wherein the circuitry is configured such that data that is not available due to a bank conflict in the first memory, is reconstructed.

3 . The apparatus of claim 1 , wherein the second memory is at least one of: separate from the first memory, or a component of the first memory.

4 . The apparatus of claim 1 , wherein the circuitry is a component of a memory controller.

5 . The apparatus of claim 1 , wherein the circuitry is further configured such that the code is stored in the second memory with the subset of the data.

6 . The apparatus of claim 1 , wherein the circuitry is further configured such that the subset of the data is identified based on a plurality of requests in connection with the subset of the data in real-time.

7 . The apparatus of claim 1 , wherein the circuitry is further configured such that, the subset of the data is identified by utilizing a flow, and the subset of the data is processed to generate the code by a memory controller, utilizing the flow.

8 . The apparatus of claim 1 , wherein the circuitry is further configured such that the subset of the data is identified based on a request in connection with the subset of the data.

9 . The apparatus of claim 8 , wherein the circuitry is further configured such that the request is identified by a scheduler outside of a memory controller.

10 . The apparatus of claim 8 , wherein the circuitry is further configured such that the subset of the data is processed, at least in part, simultaneously with a processing of the request.

11 . The apparatus of claim 1 , wherein the circuitry is further configured for receiving a message including information associated with a request in connection with the subset of the data, and the subset of the data is identified based on the information.

12 . The apparatus of claim 1 , wherein the circuitry is further configured for determining whether the first memory is scheduled for a plurality of accesses.

13 . The apparatus of claim 12 , wherein the circuitry is further configured such that the subset of the data is conditionally processed based on whether the first memory is scheduled for a plurality of accesses.

14 . The apparatus of claim 1 , wherein the circuitry is further configured for determining whether a capacity of the second memory is capable of accommodating the storage of the code.

15 . The apparatus of claim 14 , wherein the circuitry is further configured such that at least a portion of the second memory is cleared, based on the determination whether the capacity of the second memory is capable of accommodating the storage of the code.

16 . The apparatus of claim 1 , wherein the circuitry is further configured for determining whether a preparation of the second memory is ready for accommodating the storage of the code.

17 . The apparatus of claim 16 , wherein the circuitry is further configured such that the storage of the code is initiated, based on the determination whether the preparation of the second memory is ready for accommodating the storage of the code.

18 . The apparatus of claim 1 , wherein the circuitry is further configured such that the subset of the data includes first data of a first bank of the first memory and second data of a second bank of the first memory, such that the code is operable for performing one or more functions in connection with the first data of the first bank and the second data of the second bank.

19 . The apparatus of claim 1 , wherein the circuitry is further configured such that the subset of the data includes first data of a first bank of the first memory, second data of a second bank of the first memory, and third data of a third bank of the first memory; such that the code is operable for performing one or more functions in connection with the first data of the first bank, the second data of the second bank, and the third data of the third bank.

20 . The apparatus of claim 1 , wherein the apparatus is configured such that the code is operable for performing one or more functions in connection with using one or more data items from every bank of the first memory.

21 . The apparatus of claim 1 , wherein the apparatus is operable for reconstructing a plurality of simultaneous read operations in connection with a bank.

22 . A method, comprising:
identifying a subset of data stored in a first memory; processing the subset of the data stored in the first memory, to generate a code; and storing the code in a second memory, for use in reconstructing at least a portion of the data.

23 . A computer program product embodied on a non-transitory computer readable medium, comprising:
code for identifying a subset of data stored in a first memory; code for processing the subset of the data stored in the first memory, to generate a code; and code for storing the code in a second memory, for use in reconstructing at least a portion of the data.

Assignees

• Futurewei Technologies Inc

Inventors

• Luan Hao
• Gatherer Alan
• Vishwanath Sriram
• Hunger Casen
• Jain Hardik

Classifications

• G06F11/1012 Primary

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

• G06F2201/84

  Using snapshots, i.e. a logical point-in-time copy of the data · CPC title

• G06F11/1088 Primary

  Reconstruction on already foreseen single or plurality of spare disks · CPC title

• G06F11/1448

  Management of the data involved in backup or backup restore · CPC title

• G06F11/108 Primary

  Parity data distribution in semiconductor storages, e.g. in SSD · CPC title