Methods and Apparatus for Compensation and Current Spreading Correction in Shared Drain Multi-Channel Load Switch

Patent metadata

Field	Value
Publication number	US-2017030948-A1
Application number	US-201615211450-A
Country	US
Kind code	A1
Filing date	Jul 15, 2016
Priority date	Jul 31, 2015
Publication date	Feb 2, 2017
Grant date	—

Abstract

Described example embodiments include an integrated circuit having a first channel area with a first FET formed in a semiconductor substrate, the substrate providing a contact to the drain. A second channel area includes a second FET formed in the semiconductor substrate. A pilot FET couples to the first FET in a current mirror configuration. A third FET has a conductivity opposite the first and second FETs and couples to the source of the pilot FET. An op amp includes an output coupled to the gate of the third FET. Signals from the drain of the second FET and the source of the pilot FET couple to the inverting input of the op amp. Signals from the source of the first FET and the drain of the first FET couple to the non-inverting input of the op amp. Methods and additional apparatus are disclosed.

First claim

What is claimed is:

1 . An integrated circuit, comprising:
a first channel area having a first FET of a first conductivity type formed in a semiconductor substrate, the first FET having at least one source, at least one gate and a drain, the semiconductor substrate providing a contact to the drain; a second channel area having a second FET of the first conductivity type formed in the semiconductor substrate and the second FET having at least one source, at least one gate and a drain, the semiconductor substrate providing a contact to the drain of the second FET; a pilot FET formed in the first channel area having a drain coupled to the drain of the first FET, a gate coupled to the gate of the first FET, and a source; an op amp having an output, an inverting input and a non-inverting input; a first summing node coupled to the inverting input of the op amp and coupled to the source of the pilot FET and to the drain of the second FET; a second summing node coupled to the non-inverting input of the op amp and coupled to the source of the first FET and to the drain of the first FET; and a third FET having a conductivity opposite the first and second FETs, and having a gate coupled to the output of the op amp, a source coupled to the source of the pilot FET, and a drain coupled to a current sensing output terminal.

2 . The integrated circuit of claim 1 , in which the first and second FETs are N-channel FETs.

3 . The integrated circuit of claim 1 , in which the third FET is a P-channel FET.

4 . The integrated circuit of claim 1 and further including a current measurement circuit having a first terminal coupled to the source of the third FET.

5 . The integrated circuit of claim 1 and further including:
a first resistor having a first terminal coupled to the drain of the second FET and a second terminal coupled to the first summing node;
a second resistor having a first terminal coupled to the source of the pilot FET and a second terminal coupled to the first summing node;
a third resistor having a first terminal coupled to the drain of the first FET and a second terminal coupled to the second summing node; and
a fourth resistor having a first terminal coupled to the source of the first FET and a second terminal coupled to the second summing node.

6 . The integrated circuit of claim 5 in which the first resistor and the third resistor are trimmable.

7 . The integrated circuit of claim 5 , in which:
the source of the pilot FET is coupled to the drain of the third FET by a first transistor; the second terminal of the first resistor is coupled to the first summing node through a second transistor; the first summing node is coupled to the inverting input of the op amp through a third transistor; the second terminal of the second resistor is coupled to the first summing node; the second terminal of the third transistor is coupled to the second summing node through a fourth transistor; the second terminal of the fourth resistor is coupled to the second summing node; the second summing node is coupled to the non-inverting input of the op amp by a fifth transistor; and the first, second, third, fourth and fifth transistors each have a gate terminal selectively coupled to enable a current through the pilot FET to flow through the third FET.

8 . The integrated circuit of claim 7 , in which at least the second, third, fourth and fifth transistors are extended drain transistors.

9 . The integrated circuit of claim 1 , and including a second pilot FET in the second channel area coupled to the second FET in a current mirror configuration.

10 . The integrated circuit of claim 1 , in which the first FET and the second FET are vertical power FET devices.

11 . An apparatus, comprising:
a first channel area having a first FET of a first conductivity type formed in a semiconductor substrate, the first FET having at least one source, a gate and a drain, the semiconductor substrate providing a contact to the drain, the semiconductor substrate further providing a terminal for receiving a drain potential; a second channel area having a second FET of the first conductivity type formed in the semiconductor substrate, the second FET having at least one source, a gate and a drain, the semiconductor substrate providing a contact to the drain; a first pilot FET formed in the first channel area having a drain coupled to the drain of the first FET, a gate coupled to the gate of the first FET, and a source; a second pilot FET formed in the second channel area having a drain coupled to the drain of the second FET, a gate coupled to the gate of the second FET, and a source; a third FET having a conductivity type opposite the first conductivity type, and having a source switchably coupled to one of the drain of the first pilot FET and the drain of the second pilot FET, and having a gate and a source coupled to a current sensing output terminal; an op amp having an output coupled to the gate of the third FET, an inverting input and a non-inverting input; a first summing node coupled to the inverting input of the op amp and being switchably coupled to one of the source of the first pilot FET and the source of the second pilot FET, and further being switchably coupled to one of the drain of the second FET and the drain of the first FET; and a second summing node coupled to the non-inverting input of the op amp and being switchably coupled to one of the source of the first FET and the source of the second FET, and further being switchably coupled to one of the drain of the first FET and the drain of the second FET.

12 . The apparatus of claim 11 , and further comprising:
a first resistor having a first terminal coupled to the drain of the second FET and a second terminal coupled to the first summing node, the first resistor being trimmable; a second resistor having a first terminal coupled to the source of the first pilot FET and a second terminal coupled to the first summing node; a third resistor having a first terminal coupled to the source of the first FET and a second terminal coupled to the second summing node; and a fourth resistor having a first terminal coupled to the drain of the first FET and a second terminal coupled to the second summing node, the fourth resistor being trimmable.

13 . The apparatus of claim 12 , and further comprising:
a fifth resistor having a first terminal coupled to the drain of the first FET and a second terminal coupled to the first summing node, the fifth resistor being trimmable; a sixth resistor having a first terminal coupled to the source of the second pilot FET and a second terminal coupled to the first summing node; a seventh resistor having a first terminal coupled to the source of the second FET and a second terminal coupled to the second summing node; and an eighth resistor having a first terminal coupled to the drain of the second FET via an eighth switch and a second terminal coupled to the second summing node, the eight resistor being trimmable.

14 . The apparatus of claim 11 having a first load coupled to the source of the first FET and having a second load coupled to the source of the second FET.

15 . The apparatus of claim 11 in which the first and second FETs and the first and second pilot FETs are N-channel FETs.

16 . The apparatus of claim 11 and further including a current measurement load having a first terminal coupled to the source of the third FET and a second terminal coupled to a second potential.

17 . A method for measuring current in a first FET formed in a first channel area of

Assignees

• Texas Instruments Inc

Inventors

• Baldwin David J
• Roman Hector X
• Rahman Md Abidur

Classifications

• G01R19/10 Primary

  Measuring sum, difference or ratio · CPC title

• H01L27/088

  Electricity · mapped topic

• H01L29/41741

  Electricity · mapped topic

• H10D30/66

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D84/83 Primary

  of only insulated-gate FETs [IGFET] · CPC title