Semiconductor memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2017018565-A1
Application number	US-201614986853-A
Country	US
Kind code	A1
Filing date	Jan 4, 2016
Priority date	Jul 14, 2015
Publication date	Jan 19, 2017
Grant date	—

Abstract

According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a first insulating layer. The plurality of control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The first insulating layer is positioned between the semiconductor layer and the control gate electrode. In addition, part of the first insulating layer is a charge accumulation layer. Moreover, part of the first insulating layer is an oxide layer positioned upwardly of the charge accumulation layer.

First claim

What is claimed is:

1 . A semiconductor memory device, comprising:
a plurality of control gate electrodes stacked above a substrate; a semiconductor layer having as its longitudinal direction a direction perpendicular to the substrate, the semiconductor layer facing the plurality of control gate electrodes; and a first insulating layer positioned between the semiconductor layer and the control gate electrode, part of the first insulating layer being a charge accumulation layer, and part of the first insulating layer being an oxide layer positioned upwardly of the charge accumulation layer.

2 . The semiconductor memory device according to claim 1 , further comprising:
a second insulating layer positioned between the semiconductor layer and the first insulating layer; and a third insulating layer provided between the first insulating layer and the control gate electrode.

3 . The semiconductor memory device according to claim 1 , wherein
the plurality of control gate electrodes include a first control gate electrode and a second control gate electrode positioned more upwardly than the first control gate electrode, and a boundary of the charge accumulation layer and the oxide layer is positioned more upwardly than the first control gate electrode and more downwardly than an upper surface of the second control gate electrode.

4 . The semiconductor memory device according to claim 3 , comprising:
a memory string including a plurality of memory cells connected in series; and a select gate transistor connected to one end of the memory string, wherein the first control gate electrode functions as a control gate electrode of the memory cell, and the second control gate electrode functions as a control gate electrode of the select gate transistor.

5 . The semiconductor memory device according to claim 4 , wherein
the plurality of control gate electrodes include a plurality of the second control gate electrodes, and the boundary of the charge accumulation layer and the oxide layer is positioned more downwardly than a lower surface of the second control gate electrode positioned in a lowermost layer.

6 . The semiconductor memory device according to claim 4 , further comprising
a dummy memory cell provided between the memory cell and the select gate transistor, wherein the plurality of control gate electrodes further include a third control gate electrode positioned between the first control gate electrode and the second control gate electrode, and the third control gate electrode functions as a control gate electrode of the dummy memory cell.

7 . The semiconductor memory device according to claim 1 , wherein
a boundary of the charge accumulation layer and the oxide layer is positioned more downwardly the closer a position of the boundary is to the semiconductor layer and more upwardly the closer the position of the boundary is to the control gate electrode.

8 . The semiconductor memory device according to claim 3 , wherein
the boundary of the charge accumulation layer and the oxide layer is positioned more downwardly the closer a position of the boundary is to the semiconductor layer and more upwardly the closer the position of the boundary is to the control gate electrode, a lower end of the boundary is positioned more upwardly than the first control gate electrode, and an upper end of the boundary is positioned more downwardly than the upper surface of the second control gate electrode.

9 . A method of manufacturing a semiconductor memory device, the semiconductor memory device comprising:
a plurality of control gate electrodes stacked above a substrate; a semiconductor layer having as its longitudinal direction a direction perpendicular to the substrate, the semiconductor layer facing the plurality of control gate electrodes; and a charge accumulation layer positioned between the control gate electrode and the semiconductor layer, the method comprising: alternately stacking a plurality of inter-layer insulating layers and first layers above the substrate; forming an opening that penetrates the plurality of inter-layer insulating layers and first layers; forming the charge accumulation layer in the opening; oxidizing an upper portion of the charge accumulation layer; and forming the semiconductor layer in the opening.

10 . The method of manufacturing a semiconductor memory device according to claim 9 , comprising:
after forming the semiconductor layer, forming a trench that divides at least part of the plurality of inter-layer insulating layers and first layers; removing the first layer via the trench; and forming the control gate electrode between the first insulating layers adjacent in the direction perpendicular to the substrate.

11 . The method of manufacturing a semiconductor memory device according to claim 9 , wherein
oxidation of the upper portion of the charge accumulation layer is performed by a plasma oxidation method.

Assignees

• Toshiba Kk

Inventors

• Nishida Daisuke
• Sekine Katsuyuki
• Ishigaki Hirokazu
• Shimura Yasuhiro

Classifications

• H10P14/6532

  by exposure to a plasma · CPC title

• H10P14/6522

  introduced into a nitride material, e.g. changing SiN to SiON · CPC title

• H10P14/6319

  Formation by plasma treatments, e.g. plasma oxidation of the substrate · CPC title

• H10P14/6304

  Formation by oxidation, e.g. oxidation of the substrate · CPC title

• H01L27/11556

  Electricity · mapped topic