Temperature stable reference current

Patent metadata

Field	Value
Publication number	US-2017017253-A1
Application number	US-201514936927-A
Country	US
Kind code	A1
Filing date	Nov 10, 2015
Priority date	Jul 16, 2015
Publication date	Jan 19, 2017
Grant date	—

Abstract

A circuit for generating a constant current includes a first current generator that conducts a first current based upon a supply voltage and a resistive element and that generates a first mirrored current based on the current, a second current generator that generates a second current based on the first current wherein the second mirrored current decreases as the current increases and decreases as the current increases and a summing circuit for summing currents proportional to said first and second currents to generate an output current.

First claim

What is claimed is:

1 . A circuit for generating a constant current, comprising:
a first current generator that conducts a first current based upon a supply voltage and a resistive element and that generates a first mirrored current based on the current; a second current generator that generates a second current based on the first current wherein the second mirrored current decreases as the current increases and decreases as the current increases; and a summing circuit for summing currents proportional to said first and second currents to generate an output current.

2 . The circuit of claim 1 , wherein the summing circuit comprises:
a first current mirror for providing a first mirrored current proportional to the first current; a second current mirror for providing a second mirrored current proportional to the second current; and a summing device for summing the first and second mirrored currents to provide a first reference current.

3 . The circuit of claim 2 , further comprising:
an output current mirror for providing a second reference current proportional to the first reference current.

4 . The circuit for generating the constant current of claim 1 wherein the third mirrored current changes approximately 10% or less in relation to changes in of the current due to either loading or circuit temperature changes.

5 . The circuit for generating the constant current of claim 1 wherein the current based on the supply voltage and the resistive element increases with temperature increases.

6 . The circuit for generating the constant current of claim 1 wherein the current based on the supply voltage and resistive element increases as much as 20% with temperature increases.

7 . The circuit for generating the constant current of claim 1 wherein the third mirrored current changes no more than 2% for a 20% change in the current due to temperature changes.

8 . The circuit for generating the constant current of claim 1 wherein the second mirrored current decreases as a circuit temperature increases.

9 . The circuit for generating the constant current of claim 1 wherein the first current minor uses n-channel MOSFETs and the third current mirror uses p-channel MOSFETs or the first current mirror uses p-channel MOSFETs and the third current mirror uses n-channel MOSFETs.

10 . The circuit for generating the constant current of claim 7 wherein the second current minor uses the same type of MOSFETs as the first current minor.

11 . The circuit for generating the constant current of claim 1 wherein the third current mirror comprises at least two MOSFETs that generate two constant current source outputs based on the sum of the first and second mirrored currents.

12 . The circuit for generating the constant current of claim 1 further comprising a current generator circuit configured to generate an inverse current that decreases for temperature increases and that increases for temperature decreases.

13 . The circuit for generating the constant current of claim 10 wherein the second mirrored current is based upon the inverse current generated by the current generator circuit.

14 . A system for generating a constant reference current, comprising:
a first current generator configured to generate a first current; a first current mirror that generates a first mirrored current based on the first current; a second current generator that generates a second current; a second current mirror that generates a second mirrored current based on the second current; and a third current mirror that generates a reference current based on a sum of the first and second mirrored currents.

15 . The system of claim 12 wherein the second current generator is configured to decrease a magnitude of the second current based upon at least one of an increase in temperature and an increase in the first current.

16 . The system of claim 13 wherein the second current generator decreases the second current based on increases in the first current and, inversely, increases the second current based on decreases in the first current.

17 . A method in a circuit configured for generating a substantially constant reference current course, comprising:
generating a first current; generating a first mirrored current based on the first current; generating a second current; generating a second mirrored current based on the second current; and generating a reference current based on a sum of the first and second mirrored currents.

18 . The method of claim 15 further including decreasing the second current based upon at least one of an increase in temperature and an increase in the first current.

19 . The method of claim 15 further including decreasing the second mirrored current based on increases in the first current and, inversely, increasing the second mirrored current based upon decreases in the first current.

20 . The method of claim 15 wherein the reference current changes no more than 10 percent in relation to changes in the first current.

21 . The method of claim 15 further including generating first and second reference currents based on the sum of the first and second mirrored currents.

22 . The method of claim 15 further including generating the first current based upon a voltage and a current setting resistive element.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Onishi Akinobu

Classifications

• G05F3/262 Primary

  using field-effect transistors only · CPC title