Array substrate and organic light-emitting display including the same

Patent metadata

Field	Value
Publication number	US-2017012063-A1
Application number	US-201615273478-A
Country	US
Kind code	A1
Filing date	Sep 22, 2016
Priority date	Jun 17, 2013
Publication date	Jan 12, 2017
Grant date	—

Abstract

An array substrate includes a substrate, a barrier layer disposed on the substrate, a buffer layer disposed on the barrier layer, a first insulating layer disposed on the buffer layer, a second insulating layer disposed on the first insulating layer, a plurality of wiring patterns disposed between the first insulating layer and the second insulating layer and/or on the second insulating layer. In addition, the wiring patterns are separated from each other, and extend toward a side of the substrate. The array substrate further includes a recess pattern disposed adjacent the wiring patterns and recessed from a top surface of the second insulating layer to expose at least part of a top surface of the substrate, and an organic insulating layer disposed on the second insulating layer and exposing at least part of a portion of the top surface of the substrate which is exposed by the recess pattern.

First claim

What is claimed is:

1 . An array substrate comprising:
a substrate; an insulating layer disposed on the substrate; a plurality of wiring patterns disposed on the insulating layer, and wherein the wiring patterns are separated from each other, and extend toward a side of the substrate; and a recess pattern disposed adjacent to the plurality of wiring patterns.

2 . The array substrate of claim 1 , wherein the recess pattern exposes at least part of the top surface of the substrate.

3 . The array substrate of claim 2 , further comprising an organic layer disposed on the insulating layer.

4 . The array substrate of claim 3 , wherein the organic layer exposes at least part of a portion of the top surface of the substrate which is exposed by the recess pattern.

5 . The array substrate of claim 3 , wherein the organic insulating layer covers the portion of the top surface of the substrate which is exposed by the recess pattern.

6 . The array substrate of claim 1 , further comprising a plurality of recess pattern and the plurality of recess patterns are disposed between plurality of the wiring patterns.

7 . The array substrate of claim 1 , wherein each of the wiring patterns comprises:
a wiring line; a wiring pad, wherein the wiring pad has an end overlapping at least part of the wiring line, and has another end wider than the wiring line; and a wiring connection portion in which the wiring line and the wiring pad contact each other and are electrically connected to each other.

8 . The array substrate of claim 7 , wherein the recess pattern is disposed between adjacent wiring lines and extends to between adjacent wiring pads.

9 . The array substrate of claim 8 , wherein a width of the recess pattern disposed between the adjacent wiring lines is greater than a width of the recess pattern disposed between the adjacent wiring pads.

10 . The array substrate of claim 7 , wherein the wiring line extends in a zigzag shape, and wherein at least one of the recess patterns is disposed between adjacent wiring lines.

11 . The array substrate of claim 10 , wherein the plurality of recess patterns are disposed between a plurality of wiring lines and are arranged in a matrix of a plurality of columns and a plurality of rows.

12 . The array substrate of claim 7 , further comprising a recess groove disposed inside the wiring pad and penetrating through the wiring pad.

13 . The array substrate of claim 7 , wherein the recess pattern is disposed outside an outermost wiring line among the wiring lines.

14 . The array substrate of claim 13 , further comprising a cell ID pattern disposed outside the outermost wiring line among the wiring lines, wherein the recess pattern is disposed along an outer circumference of the cell ID pattern.

15 . The array substrate of claim 1 , further comprising at least one cutting line which traverses at least part of the substrate and is defined on the substrate, and wherein the recess pattern is disposed adjacent to the cutting line.

16 . The array substrate of claim 1 , wherein the substrate is a flexible substrate.

Assignees

• Samsung Display Co Ltd

Inventors

• Kwak Won Kyu

Classifications

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10W70/68

  Shapes or dispositions thereof · CPC title

• H10W70/695

  Organic materials · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/411

  characterised by materials, geometry or structure of the substrates · CPC title