Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-2017012000-A1
Application number	US-201514844004-A
Country	US
Kind code	A1
Filing date	Sep 3, 2015
Priority date	Jul 6, 2015
Publication date	Jan 12, 2017
Grant date	—

Abstract

A semiconductor device and a method of fabricating the same, the semiconductor device including a fin structure, a first liner, a first insulating layer and a dummy gate structure. The fin structure is disposed on a substrate, where the fin structure has a trench. The first liner disposed in the trench. The first insulating layer disposed on the first liner. The dummy gate structure is disposed on the first insulating layer and disposed above the trench, where a bottom surface of the dummy gate and a top surface of the fin structure are on a same level.

First claim

1 . A semiconductor device, comprising:
a fin structure disposed on a substrate, wherein the fin structure has a trench; a first liner disposed in the trench; a first insulating layer disposed on the first liner; a shallow trench isolation disposed in the substrate and surrounding the fin structure, wherein a bottom surface of the shallow trench isolation is higher than a bottom surface of the first insulating layer; and a dummy gate structure disposed on the first insulating layer and disposed right above the trench, wherein a bottom surface of the dummy gate structure and a top surface of the fin structure are on a same level.

2 . (canceled)

3 . The semiconductor device according to claim 1 , wherein the shallow trench isolation has a depth greater than a depth of the trench.

4 . The semiconductor device according to claim 1 , wherein the dummy gate structure further comprises:
a dummy gate electrode disposed on the trench, wherein a portion of the dummy gate electrode is in the trench; and a spacer disposed on the fin structure, surrounding the dummy gate electrode.

5 . The semiconductor device according to claim 4 , further comprising:
a second liner disposed between the spacer of the dummy gate structure and the top surface of the fin structure.

6 . The semiconductor device according to claim 1 , wherein a top surface of the first liner, a top surface of the first insulating layer and the top surface of the fin structure are on a same level.

7 . The semiconductor device according to claim 1 , further comprising a contact etching stop layer disposed on the fin structure and on the dummy gate structure.

8 . The semiconductor device according to claim 1 , further comprising at least one gate structure disposed on the fin structure.

9 . The semiconductor device according to claim 8 , further comprising at least one contact plug electrically contacted to the gate structure.

10 . A method for forming a semiconductor device, comprising:
providing a substrate having a fin structure disposed thereon, wherein the fin structure has a trench; forming a first liner in the trench; forming a first insulating layer on the first liner; and forming a dummy gate structure on the first insulating layer and disposed above the trench, wherein a bottom surface of the dummy gate structure and a top surface of the fin structure are on a same level.

11 . The method of claim 10 , further comprising forming a shallow trench isolation in the substrate, and surrounding the fin structure.

12 . The method of claim 11 , wherein the shallow trench isolation has a depth greater than a depth of the trench.

13 . The method of claim 10 , wherein the dummy gate structure further comprises:
a dummy gate electrode disposed on the trench, wherein a portion of the dummy gate electrode is in the trench; and a spacer disposed on the fin structure, surrounding the dummy gate electrode.

14 . The method of claim 13 , further comprising:
forming a second liner between the spacer of the dummy gate structure and the top surface of the fin structure.

15 . The method of claim 10 , wherein a top surface of the first liner, a top surface of the first insulating layer and the top surface of the fin structure are on a same level.

16 . The method of claim 10 , further comprising forming a contact etching stop layer on the fin structure and on the dummy gate structure.

17 . The method of claim 10 , further comprising forming at least one gate structure on the fin structure.

18 . The method of claim 17 , further comprising forming at least one contact plug electrically contacted to the gate structure.

Assignees

• United Microelectronics Corp

Inventors

• Tseng I-Ming
• Liang Wen-An
• Huang Chen-Ming

Classifications

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D84/834

  comprising FinFETs · CPC title