Electronic device and method of manufacturing the same
US-2024404904-A1 · Dec 5, 2024 · US
US2017005155A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2017005155-A1 |
| Application number | US-201615053918-A |
| Country | US |
| Kind code | A1 |
| Filing date | Feb 25, 2016 |
| Priority date | Jul 3, 2015 |
| Publication date | Jan 5, 2017 |
| Grant date | — |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A display apparatus includes a pixel having a first area emitting light and a second area transmitting light. A pixel circuit unit is in the first area and includes a thin film transistor. An inorganic insulation layer is in the second area. A first insulation layer covers the pixel circuit unit in the first area, and has an opening exposing the inorganic insulation layer in the second area. A first electrode is on the first insulation layer in the first area. The first electrode is electrically connected to the pixel circuit unit. A second insulation layer covers edges of the first electrode and is outside the opening formed in the first insulation layer. A second electrode is in the first area. An intermediate layer, including an emissive layer, is between the first electrode and the second electrode.
Opening claim text (preview).
What is claimed is: 1 . A display apparatus comprising: a pixel including a first area, from which light is emitted, and a second area, through which ambient light is transmitted; a pixel circuit unit disposed in the first area of the pixel and including at least one thin film transistor; an inorganic insulation layer disposed in the second area of the pixel; a first insulation layer covering the pixel circuit unit in the first area, and having an opening exposing at least a portion of the inorganic insulation layer in the second area; a first electrode disposed on the first insulation layer in the first area, wherein the first electrode is electrically connected to the pixel circuit unit; a second insulation layer covering one or more edges of the first electrode, and the second insulation layer being disposed outside of the opening formed in the first insulation layer; a second electrode disposed in the first area; and an intermediate layer disposed between the first electrode and the second electrode, the intermediate layer including an emissive layer. 2 . The display apparatus of claim 1 , wherein the first insulation layer comprises an organic insulation layer. 3 . The display apparatus of claim 1 , wherein the second insulation layer comprises an organic insulation layer. 4 . The display apparatus of claim 1 , wherein the second insulation layer has a shape of a closed loop as it covers the one or more edges of the first electrode. 5 . The display apparatus of claim 1 , wherein a concave or convex pattern is formed on an upper surface of the first insulation layer. 6 . The display apparatus of claim 1 , wherein at least a portion of the pixel circuit unit overlaps the first electrode. 7 . The display apparatus of claim 1 , wherein the inorganic insulation layer has a single layer structure or a double layer structure and the inorganic insulation layer includes silicon dioxide (SiO 2 ) and/or silicon nitride (SiN x ). 8 . The display apparatus of claim 1 , wherein the thin film transistor comprises: an active layer; a gate electrode disposed on the active layer and insulated from the active layer; a third insulation layer disposed between the active layer and the gate electrode; a plurality of fourth insulation layers disposed on the gate electrode; a source electrode disposed on the plurality of fourth insulation layers and electrically connected to the active layer; and a drain electrode disposed on the plurality of fourth insulation layers and electrically connected to the active layer. 9 . The display apparatus of claim 8 , wherein each of the source electrode and the drain electrode comprise: a bottom electrode, comprising a first conductive material; and a top electrode, comprising a second conductive material. 10 . The display apparatus of claim 9 , wherein the second conductive material comprises a transparent conductive material. 11 . The display apparatus of claim 8 , wherein the third insulation layer and the inorganic insulation layer comprises a same material. 12 . The display apparatus of claim 8 , further comprising a capacitor including: a first capacitor electrode disposed on a same layer as the gate electrode; a second capacitor electrode disposed between the insulation layers of the plurality of fourth insulation layers; and a third capacitor electrode disposed on a same layer as the source electrode and the drain electrode. 13 . The display apparatus of claim 1 , further comprising a transparent conductive layer disposed on at least a portion of the inorganic insulation layer. 14 . The display apparatus of claim 13 , wherein the first insulation layer covers at least a portion of the transparent conductive layer. 15 . The display apparatus of claim 13 , wherein the transparent conductive layer covers an entirety of an upper surface of the inorganic insulation layer. 16 . The display apparatus of claim 13 , wherein the thin film transistor comprises: an active layer; a gate electrode disposed on the active layer and insulated from the active layer; a third insulation layer disposed between the active layer and the gate electrode; a plurality of fourth insulation layers disposed on the gate electrode; a source electrode disposed on the plurality of fourth insulation layers and electrically connected to the active layer; and a drain electrode disposed on the plurality of fourth insulation layers and electrically connected to the active layer. 17 . The display apparatus of claim 16 , further comprising a capacitor including: a first capacitor electrode disposed on a same layer as the gate electrode; a second capacitor electrode disposed between insulation layers of the plurality of fourth insulation layers; and a third capacitor electrode disposed on a same layer as the source electrode and the drain electrode. 18 . The display apparatus of claim 17 , wherein each of the gate electrode and the first capacitor electrode comprises: a bottom electrode, comprising a first conductive material; and a top electrode, comprising a second conductive material. 19 . The display apparatus of claim 18 , wherein the first conductive material and the transparent conductive layer comprise a same material. 20 . The display apparatus of claim 16 , wherein the third insulation layer comprises a same material as the inorganic insulation layer. 21 . A method for manufacturing a display apparatus, comprising: disposing a buffer layer on a substrate; forming a semiconductor layer on the buffer layer, over a first area of the substrate; forming a first insulation layer on the buffer layer and the semiconductor layer; forming a first conductive layer over the first insulation layer; patterning the first conductive layer to form: a gate electrode of a thin film transistor (TFT) over the first area of the substrate; and a first capacitor electrode of a capacitor over the first area of the substrate; doping the semiconductor layer, using the gate electrode as a mask, to dope B or P ion impurities into a source and drain area of the semiconductor layer, leaving an un-doped region of the semiconductor layer, between the source and drain areas, as a channel area; forming a second insulation layer over the patterned first conductive layer; forming a second conductive layer on the second insulation layer; patterning the second conductive layer to form a second capacitor electrode of the capacitor over the first area; forming a third insulation layer over the second capacitor electrode and the second insulation layer; patterning the third insulation layer together with the first and second insulation layers to expose a part of the first insulation layer of a second area of the substrate to form an inorganic insulation layer and to form contact holes that expose portions of the source and drain areas; forming a third conductive layer and a fourth conductive layer over the third insulation layer; patterning the third and fourth conductive layers, simultaneously, to form a source electrode in contact with the source area, a drain electrode in contact with the drain area, to form a third capacitor electrode of the capacitor, and to form a pad electrode over a pad area of the substrate; forming a fourth insulation layer over the third, fourth patterned conductive layers and the inorganic insulation layer; patterning the fourth insulation layer to expose the source electrode or the drain electrode, the pad e
by chemical means · CPC title
by chemical means · CPC title
Manufacture or treatment · CPC title
comprising silicon, e.g. amorphous silicon or polysilicon · CPC title
further characterised by the dopants · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.