Electronic device

Patent metadata

Field	Value
Publication number	US-2017005137-A1
Application number	US-201514958665-A
Country	US
Kind code	A1
Filing date	Dec 3, 2015
Priority date	Jul 3, 2015
Publication date	Jan 5, 2017
Grant date	—

Abstract

An electronic device may include a semiconductor memory. The semiconductor memory may include a stack in which a plurality of dielectric layers and a plurality of first electrodes are alternately stacked over a substrate in a vertical direction relative to the substrate; a hole pattern passing through the stack in the vertical direction and having a polygonal shape when viewed in a plan view; a plurality of second electrodes disposed on respective sidewalls of the hole pattern; and a plurality of variable resistance layers interposed between the plurality of second electrodes and the plurality of horizontal electrodes.

First claim

What is claimed is:

1 . An electronic device including a semiconductor memory, the semiconductor memory comprising:
a stack in which a plurality of dielectric layers and a plurality of first electrodes are alternately stacked over a substrate in a vertical direction relative to the substrate; a hole pattern passing through the stack in the vertical direction and having a polygonal shape when viewed in a plan view; a plurality of second electrodes disposed on respective sidewalls of the hole pattern; and a plurality of variable resistance layers interposed between the plurality of second electrodes and the plurality of horizontal electrodes.

2 . The electronic device of claim 1 , wherein the second electrodes extend in the vertical direction and contact the substrate.

3 . The electronic device of claim 1 , wherein the variable resistance layers include a transition metal oxide, a perovskite-based material, a phase change material, a chalcogenide-based material, a ferroelectric material, or a ferromagnetic material.

4 . The electronic device of claim 1 , wherein the first electrodes and the second electrodes include any one transition metal or nitride selected from the group consisting of TiN, Pt, W, TaN, Ir, Ni, Cu, Ta, Ti, Hf, Zr, and a combination thereof.

5 . The electronic device of claim 1 , wherein the length of the first electrode is shorter than the length of the dielectric layer so that grooves are formed between the first electrodes and the second electrodes, and the variable resistance layers are disposed in the grooves.

6 . The electronic device of claim 5 , wherein the variable resistance layers are disposed along internal walls of the grooves.

7 . The electronic device of claim 6 , wherein each of the second electrode comprises a plurality of projections filling the remaining portions of grooves in which variable resistance layers are disposed, at each of the sidewalls of the hole pattern.

8 . The electronic device of claim 1 , wherein each of the dielectric layer and the first electrode has a closed loop shape when viewed in a plan view and surrounds the hole pattern and the second electrodes.

9 . The electronic device of claim 1 , wherein the semiconductor memory comprises a plurality of cell arrays, each cell array being disposed along a corresponding one of the sidewalls of the hole pattern.

10 . The electronic device of claim 9 , wherein the hole pattern is a quadrangular hole pattern having four sidewalls.

11 . The electronic device according to claim 1 , further comprising a microprocessor which includes:
a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor; an operation unit configured to perform an operation based on a result that the control unit decodes the command; and a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed, wherein the semiconductor memory unit that includes the resistance variable element is part of the memory unit in the microprocessor.

12 . The electronic device according to claim 1 , further comprising a processor which includes:
a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data; a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit, wherein the semiconductor memory unit that includes the resistance variable element is part of the cache memory unit in the processor.

13 . The electronic device according to claim 1 , further comprising a processing system which includes:
a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command; an auxiliary memory device configured to store a program for decoding the command and the information; a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside, wherein the semiconductor memory unit that includes the resistance variable element is part of the auxiliary memory device or the main memory device in the processing system.

14 . The electronic device according to claim 1 , further comprising a data storage system which includes:
a storage device configured to store data and conserve stored data regardless of power supply; a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside; a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside, wherein the semiconductor memory unit that includes the resistance variable element is part of the storage device or the temporary storage device in the data storage system.

15 . The electronic device according to claim 1 , further comprising a memory system which includes:
a memory configured to store data and conserve stored data regardless of power supply; a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside; a buffer memory configured to buffer data exchanged between the memory and the outside; and an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside, wherein the semiconductor memory unit that includes the resistance variable element is part of the memory or the buffer memory in the memory system.

Assignees

• Sk Hynix Inc

Inventors

• Kim Kyung-Wan

Classifications

• G06F2212/225

  Hybrid cache memory, e.g. having both volatile and non-volatile portions · CPC title

• G06F2212/222

  Non-volatile memory · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/0846 Primary

  Cache with multiple tag or data arrays being simultaneously accessible · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title