Integrated cantilever switch

Patent metadata

Field	Value
Publication number	US-2016380118-A1
Application number	US-201615260206-A
Country	US
Kind code	A1
Filing date	Sep 8, 2016
Priority date	Mar 31, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm 2 .

First claim

1 . A method, comprising:
forming a layered stack on a silicon substrate, the layered stack including at least a first and a second semiconducting material in an alternating arrangement; forming a transistor gate structure overlying the layered stack; forming raised source and drain regions on sides of the transistor gate structure; forming a cavity by forming openings in the raised source and drain regions, the forming of the openings exposing a top surface of the layered stack; forming a movable member of the second semiconducting material in the cavity by selectively removing portions of the first semiconductor material from the layered stack; and sealing the openings to the cavity.

2 . The method of claim 1 wherein forming the raised source and drain regions includes forming the raised source and drain regions to be faceted.

3 . The method of claim 1 wherein forming the moveable member includes forming the moveable member to be a cantilever arm.

4 . The method of claim 1 wherein sealing the openings includes forming a spin-on glass material in the openings.

5 . The method of claim 1 wherein forming the gate structure includes a metal gate, a high-k gate dielectric, and insulating sidewall spacers.

6 . The method of claim 1 wherein forming the layered stack on the silicon substrate includes forming the first and second semiconducting materials from one or more of silicon and silicon germanium.

7 . The method of claim 1 wherein forming the transistor gate structure includes forming a dielectric layer on the top surface of the layer stack, forming a conductive layer on the dielectric layer, and forming sidewalls on adjacent to the conductive layer.

8 . The method of claim 1 , further comprising forming a metal tip on the moveable member.

9 . The method of claim 1 wherein forming the movable member of the second semiconducting material includes exposing the first semiconductor material from the layered stack to hydrochloric acid.

10 . A method, comprising:
forming a layered stack overlying a silicon substrate, the layered stack including a first, a second, and a third layer of semiconductor material; forming a flexible member that extends from the second layer of the layered stack into a cavity by removing portions of the first and third layer of semiconductor material; forming a gate overlying the flexible member and the cavity; and forming raised source and drain regions adjacent to sides of the gate, the raised source and drain regions being on the third layer of the layered stack.

11 . The method of claim 10 , further comprising forming the cavity by:
forming a first opening in the first semiconductor material; forming a second opening in the second semiconductor material; forming a third opening in the third semiconductor material; and filling the first opening, the second opening, and the third opening with a sacrificial material; and forming the gate on the sacrificial material; and removing the sacrificial material.

12 . The method of claim 10 wherein forming raised source and drain regions includes forming the raised source and drain regions to be spaced from the gate by a distance.

13 . The method of claim 10 , further comprising forming openings between the gate and raised source and drain regions, forming the cavity by removing sacrificial material through the openings, and sealing the openings.

14 . The method of claim 10 , further comprising:
forming openings in the raised source and drain regions by selectively removing portions of the raised source and drain regions; selectively removing portions of the first, second, and third semiconductor materials from the layered stack; and filling the openings of the raised source and drain regions by forming an insulating material in the openings.

15 . A method, comprising:
forming a first layer on a substrate; forming a second layer on the first layer; forming a third layer on the second layer; forming a cavity in the first, second, and third layers; forming a moveable member having an end extending from the second layer into the cavity; forming a transistor gate structure overlying the cavity and the moveable member; forming raised source and drain regions on the layered stack; separating the raised source and drain regions from the gate structure by a first distance; and forming an insulating material between the raised source and drain regions and the gate.

16 . The method of claim 14 wherein forming the moveable member includes:
forming the moveable member to be a cantilever arm; and
forming a metal tip on the end of the cantilever arm.

17 . The method of claim 14 wherein forming the cavity includes forming a sacrificial material within the first layer, the second layer, and the third layer, and removing the sacrificial material before forming the gate structure.

18 . The method of claim 14 wherein forming the transistor gate structure includes forming a metal gate on a high-k-gate dielectric and forming insulating sidewall spacers.

Assignees

• St Microelectronics Inc

Inventors

• Liu Qing
• Zhang John H

Classifications

• H10P50/644

  Anisotropic liquid etching (H10P50/61 takes precedence) · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H01H2001/0084

  with perpendicular movement of the movable contact relative to the substrate · CPC title

• H01H50/005

  using micromechanics · CPC title

• H01H49/00

  Apparatus or processes specially adapted to the manufacture of relays or parts thereof · CPC title