Novel Fin Structure of FinFet

Patent metadata

Field	Value
Publication number	US-2016380103-A1
Application number	US-201615263021-A
Country	US
Kind code	A1
Filing date	Sep 12, 2016
Priority date	Dec 28, 2012
Publication date	Dec 29, 2016
Grant date	—

Abstract

A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa. The mesa has a first semiconductor material, and the channel has a second semiconductor material different from the first semiconductor material. The convex-shaped feature is stepped-shaped, stair-shaped, or ladder-shaped. The convex-shaped feature includes a first isolation feature disposed between the channel and the mesa, and a second isolation feature disposed between the channel and the first isolation feature. The first isolation feature is U-shaped, and the second isolation feature is rectangular-shaped. A portion of the second isolation feature is surrounded by the channel and another portion of the second isolation feature is surrounded by the first isolation feature.

First claim

What is claimed is:

1 . A method of forming a semiconductor device, the method comprising:
forming a mesa of a first semiconductor material; etching a concave portion in the mesa, the concave portion having sidewalls and a bottom surface; depositing a first insulating material on the sidewalls and the bottom surface of the concave portion; depositing a second insulating material on the first insulating material filling the concave portion; removing a portion of the first insulating material on the sidewalls of the concave portion, wherein after the removing, an uppermost surface of the second insulating material extends above an uppermost surface of the first insulating material; recessing an upper surface of the mesa, wherein after the recessing, an uppermost surface of the mesa is below the uppermost surface of the second insulating material; and depositing a channel layer of a second semiconductor material different from the first semiconductor material on the mesa, the first insulating material, and the second insulating material.

2 . The method of claim 1 , further comprising forming a gate structure over the channel layer, the gate structure being laterally above the second insulating material.

3 . The method of claim 1 , wherein a thickness of the first insulating material ranges from about 1 nm to about 10 nm.

4 . The method of claim 1 , wherein a ratio of a height of the first insulating material to a width of the first insulating material ranges from about 2 to about 99.

5 . The method of claim 1 , wherein a ratio of a height of the second insulating material to a width of the second insulating material ranges from about 1 to about 166.

6 . The method of claim 1 , wherein recessing the upper surface of the mesa comprises recessing the upper surface of the mesa below an upper surface of the first insulating material.

7 . A method of forming a semiconductor device, the method comprising:
forming a mesa of a first semiconductor material, the mesa having a recess in an upper surface; forming an isolation structure in the recess; forming a channel layer of a second semiconductor material over the mesa and the isolation structure; and forming a gate structure over the channel layer, the gate structure being aligned over the isolation structure.

8 . The method of claim 7 , wherein forming the isolation structure comprises forming a lower portion to have a first width and an upper portion to have a second width less than the first width.

9 . The method of claim 8 , wherein forming the isolation structure comprises forming a first layer of a first insulating material and a second layer of a second insulating material different than the first insulating material.

10 . The method of claim 9 , wherein the isolation structure extends above an uppermost surface of the mesa.

11 . The method of claim 10 , wherein the first insulating material extends above the uppermost surface of the mesa.

12 . The method of claim 7 , further comprising:
forming isolation regions on opposing sides of the mesa prior to forming the isolation structure; and recessing the isolation regions after forming the channel layer, wherein after recessing the isolation regions the mesa extends above the isolation regions.

13 . The method of claim 12 , wherein forming the channel layer comprises:
epitaxially growing the second semiconductor material on the first semiconductor material; and planarizing the second semiconductor material to an upper surface of the isolation regions.

14 . A method of forming a semiconductor device, the method comprising:
forming a mesa of a first semiconductor material; forming a recess in the mesa; forming an isolation structure in the recess, the isolation structure extending above an upper surface of the mesa; forming a channel layer over the mesa and the isolation structure, a thickness of the channel layer over the mesa being greater than a thickness of the channel layer over the isolation structure; and forming a gate structure over the channel layer, wherein the isolation structure is interposed between a source region of the channel layer and a drain region of the channel layer.

15 . The method of claim 14 , wherein forming the channel layer comprises forming the channel layer of a second semiconductor material different than the first semiconductor material.

16 . The method of claim 14 , wherein forming the isolation structure comprises recessing mesa after forming the isolation structure.

17 . The method of claim 16 , wherein forming the mesa comprises forming the mesa between isolation regions, and further comprising recessing the isolation regions after forming the channel layer.

18 . The method of claim 14 , wherein forming the isolation structure comprises:
forming a first isolation layer over sidewalls and a bottom of the recess; forming a second isolation layer over the first isolation layer; and recessing the first isolation layer such that the second isolation layer extends further away from the mesa than the first isolation layer.

19 . The method of claim 18 , wherein forming the channel layer comprises forming the channel layer along sidewalls of the first isolation layer.

20 . The method of claim 18 , wherein forming the channel layer comprises forming the channel layer along sidewalls of the second isolation layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Gin-Chen
• Jiang Ching-Hong
• Chen Neng-Kuo
• Sun Sey-Ping
• Wann Clement Hsingjen

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title