Diffused tip extension transistor

Patent metadata

Field	Value
Publication number	US-2016380102-A1
Application number	US-201315038969-A
Country	US
Kind code	A1
Filing date	Dec 27, 2013
Priority date	Dec 27, 2013
Publication date	Dec 29, 2016
Grant date	—

Abstract

A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.

First claim

1 . A method comprising:
forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material.

2 . The method of claim 1 , wherein the thermal processing comprises thermal processing sufficient to induce the diffusion of a dopant in the doped semiconductor material from the doped semiconductor material.

3 . The method of claim 1 , wherein the opening in the junction region comprises a first opening corresponding to a source region and a second opening corresponding to a drain region.

4 . The method of claim 3 , wherein a gate structure transverses the fin and the source region and the drain region are disposed on opposite sides of the gate structure.

5 . The method of claim 4 , wherein forming an opening comprises an anisotropic etch aligned to the gate electrode.

6 . The method of claim 5 , wherein the gate electrode comprises a sidewall spacer on each of the opposite sides of the gate structure.

7 . The method of claim 1 , wherein the doped semiconductor material comprises a N-type dopant.

8 . The method of claim 7 , wherein the N-type dopant is phosphorous at a concentration on the order of at least 1×10 19 cm −3 .

9 . The method of claim 1 , wherein forming the opening comprises forming an opening to a depth of the fin.

10 . The method of claim 1 , wherein forming the opening comprises forming an opening that extends a distance greater than a depth of the fin.

11 . The method of claim 1 , wherein forming the opening comprises forming an opening that extends a distance less than a depth of the fin.

12 . A method comprising:
forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material.

13 . The method of claim 12 , wherein forming the gate electrode comprises forming a sidewall spacer on each of the oppose sides of the gate electrode.

14 . The method of claim 13 , wherein forming the opening comprises an anisotropic etch aligned to the gate electrode.

15 . The method of claim 12 , wherein forming openings comprises forming openings to a depth of the fin.

16 . The method of claim 12 , wherein forming openings comprises forming openings that extend a distance greater than a depth of the fin.

17 . The method of claim 12 , wherein forming openings comprises forming openings that extend a distance less than a depth of the fin.

18 . The method of claim 12 , wherein the doped semiconductor material comprises a N-type dopant.

19 . The method of claim 18 , wherein the N-type dopant comprises phosphorous at a concentration on the order of at least 1×10 19 cm −3 .

20 . An apparatus comprising:
a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.

21 . The apparatus of claim 20 , further comprising a sidewall spacer on each side of the opposite sides of the gate electrode.

22 . The apparatus of claim 21 , wherein a portion of the fin underlying the sidewall spacer comprises a dopant at a concentration less than a concentration of the semiconductor filled openings

23 . The apparatus of claim 20 , wherein the dopant comprises an N-type dopant.

24 . The apparatus of claim 20 , wherein the semiconductor filled openings extend a depth of the fin.

25 . The apparatus of claim 20 , wherein the semiconductor filled openings extend a distance greater than a depth of the fin.

26 . The apparatus of claim 20 , wherein the semiconductor filled openings extend a distance less than a depth of the fin.

Assignees

• Patel Pratik
• Wiedemer Jami A
• Packan Paul A
• Intel Corp

Inventors

• Patel Pratik A
• Liu Mark Y
• Wiedemer Jami A
• Packan Paul A

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/1406

  by ion implantation · CPC title

• H10P32/171

  being group IV material · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/0241

  doping of vertical sidewalls, e.g. using tilted or multi-angled implants · CPC title