Integrated circuit structure

Patent metadata

Field	Value
Publication number	US-2016379983-A1
Application number	US-201615262574-A
Country	US
Kind code	A1
Filing date	Sep 12, 2016
Priority date	Mar 28, 2012
Publication date	Dec 29, 2016
Grant date	—

Abstract

A method for forming an integrated circuit includes forming a deep n-well (DNW) in a substrate, and forming a PMOS transistor in the DNW. The method also includes forming an NMOS transistor in the substrate and outside the DNW, and forming a reverse-biased diode. The method further includes forming an electrical path between a drain of the PMOS transistor and a gate structure of the NMOS transistor. The dissipation device is also connected to the electrical path.

First claim

What is claimed is:

1 . An integrated circuit (IC) structure comprising:
a deep n-well in a substrate; a first transistor in a p-well, wherein the first transistor is separated from the deep n-well; a second transistor directly above the deep n-well; a dissipation device in the p-well; and an electrical path between a gate of the first transistor and a drain of the second transistor, wherein the dissipation device is connected to the electrical path.

2 . The IC structure of claim 1 , wherein the dissipation device is in the substrate between the first transistor and the second transistor.

3 . The IC structure of claim 1 , further comprising a third transistor directly above the deep n-well, wherein a drain of the third transistor is connected to the electrical path.

4 . The IC structure of claim 3 , wherein a gate of the third transistor is connected to a gate of the second transistor.

5 . The IC structure of claim 1 , wherein the electrical path comprises:
a first signal line connecting the gate of the first transistor to the dissipation device; and a second signal line connecting the gate of the first transistor to the drain of the second transistor, wherein the first signal line is on a different metal level from the first signal line.

6 . The IC structure of claim 1 , further comprising a substrate pickup in the substrate, wherein the substrate pickup is configured to provide a discharge path from the dissipation device.

7 . The IC structure of claim 6 , wherein the first transistor is physically between the dissipation device and the substrate pickup.

8 . An integrated circuit (IC) structure comprising:
a deep well in a substrate; a first transistor in a first well, wherein the first well is separated from the deep well; a second transistor in a second well, wherein the second well is directly above the deep well, and the second well is separated from the first well; a dissipation device in the substrate, wherein the dissipation device is physically between the first transistor and the second transistor; and an electrical path between a gate of the second transistor and a drain of the first transistor, wherein the dissipation device is connected to the electrical path.

9 . The IC structure of claim 8 , wherein the dissipation device is in the first well.

10 . The IC structure of claim 8 , wherein the dissipation device is in the second well.

11 . The IC structure of claim 8 , further comprising a third transistor in a third well, wherein the third well is separated from the deep well.

12 . The IC structure of claim 11 , wherein the third well contacts the second well.

13 . The IC structure of claim 8 , wherein the first well has a same conductivity type as the second well.

14 . The IC structure of claim 8 , wherein the first well has a different conductivity type from a conductivity type of the second well.

15 . An integrated circuit (IC) structure comprising:
a deep well in a substrate; a first transistor in a first well, wherein the first transistor is separated from the deep well; a second transistor directly above the deep well; a dissipation device in the first well; and an electrical path between a gate of the first transistor and a drain of the second transistor, wherein the dissipation device is connected to the electrical path, and the electrical path comprises:
a first signal line connecting the gate of the first transistor to the dissipation device; and
a second signal line connecting the gate of the first transistor to the drain of the second transistor, wherein the first signal line is on a different metal level from the first signal line.

16 . The IC structure of claim 15 , further comprising a third transistor directly above the deep well.

17 . The IC structure of claim 16 , further comprising a third signal line connecting the drain of the second transistor to a drain of the third transistor.

18 . The IC structure of claim 17 , wherein the third signal line is on a same metal level as the first signal line.

19 . The IC structure of claim 15 , further comprising a substrate pickup in the substrate, wherein the substrate pickup is configured to provide a discharge path from the dissipation device.

20 . The IC structure of claim 19 , wherein the first transistor is physically between the dissipation device and the substrate pickup.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yen David
• Lin Sung-Chieh
• Hsu Kuoyuan (Peter)

Classifications

• H10P34/40

  with high-energy radiation · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D84/0191

  Manufacturing their doped wells · CPC title

• H10D84/0188

  Manufacturing their isolation regions · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title