Substrate strip

Patent metadata

Field	Value
Publication number	US-2016379937-A1
Application number	US-201615138441-A
Country	US
Kind code	A1
Filing date	Apr 26, 2016
Priority date	Jun 23, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

A substrate strip is provided. The substrate strip includes a core layer including first and second substrate regions spaced apart from each other and a dummy region between the first and second substrate regions, a first interconnection layer disposed on top surfaces of the first and second substrate regions, a second interconnection layer disposed on bottom surfaces of the first and second substrate regions, and a warpage control member provided on any one of a top surface and a bottom surface of the dummy region. The warpage control member includes a metal.

First claim

What is claimed is:

1 . A substrate strip comprising:
a core layer including first and second substrate regions spaced apart from each other and a dummy region between the first and second substrate regions; a first interconnection layer disposed on first surfaces of the first and second substrate regions; a second interconnection layer disposed on second surfaces opposite to the first surfaces of the first and second substrate regions; and a warpage control member provided on any one of a first surface and a second surface of the dummy region, wherein the warpage control member includes a metal.

2 . The substrate strip of claim 1 , wherein the warpage control member includes copper.

3 . The substrate strip of claim 1 , wherein the warpage control member is in contact with the core layer.

4 . The substrate strip of claim 1 , wherein the warpage control member is electrically insulated from the first and second interconnection layers.

5 . The substrate strip of claim 1 , wherein the warpage control member includes a same material as the first interconnection layer or the second interconnection layer.

6 . The substrate strip of claim 1 , wherein
the warpage control member is provided on the second surface of the dummy region, and the warpage control member is disposed at a same level as the second interconnection laver, relative to the core layer,

7 . The substrate strip of claim 1 , wherein
the core layer has a long axis extending in a first direction, the first and second substrate regions are spaced apart from each other in the first direction, and the dummy region extends in a second direction intersecting the first direction.

8 . The substrate strip of claim 7 , wherein the warpage control member has a rectangular shape extending in the second direction when viewed in plan view.

9 . The substrate strip of claim 7 , wherein the warpage control member includes segments spaced apart from each other and repeatedly arranged in the second direction when viewed in plan view.

10 . The substrate strip of claim 1 , further comprising:
a third interconnection layer disposed between the core layer and the second interconnection layer; and a fourth interconnection layer disposed between the core layer and the first interconnection layer.

11 . The substrate strip of claim 10 , wherein the warpage control member is disposed at a same level as one of the first to fourth interconnection layers, relative to the core layer.

12 . The substrate strip of claim 10 , wherein
the warpage control member includes a first warpage control member and a second warpage control member, the first warpage control member is disposed at a same level as the second interconnection layer, relative to the core layer, and the second warpage control member is disposed at a same level as the third interconnection layer, relative to the core layer.

13 . A substrate strip comprising:
a core layer including first and second substrate regions spaced apart from each other and a dummy region between the first and second substrate regions; a first interconnection layer disposed on top surfaces of the first and second substrate regions; a second interconnection layer disposed on bottom surfaces of the first and second substrate regions; a warpage control member disposed on a bottom surface of the dummy region; a first solder resist layer covering the first interconnection layer and a top surface of the dummy region, the first solder resist layer being in contact with the top surface of the dummy region; and a second solder resist layer covering the second interconnection layer and the warpage control member.

14 . The substrate strip of claim 13 , wherein the warpage control member has a coefficient of thermal expansion (CTE) greater than that of the core layer.

15 . The substrate strip of claim 14 , wherein the warpage control member includes a metal.

16 . The substrate strip of claim 13 , wherein the warpage control member is disposed directly on the bottom surface of the dummy region.

17 . The substrate strip of claim 13 , wherein the warpage control member includes a same material as the second interconnection layer.

18 . The substrate strip of claim 13 , wherein the warpage control member is disposed at a same level as the second interconnection layer, relative to the core layer.

19 . The substrate strip of claim 13 , wherein
the first interconnection layer includes a chip bonding pad, and the second interconnection layer includes an external connection pad.

20 . A substrate strip comprising:
a core layer including a first surface and a second surface that is opposite to the first surface; a first interconnection layer on the first surface of the core layer and including a first pad; a second interconnection layer on the second surface of the core layer and including a second pad; and a warpage control member on one of the first surface and the second surface of the core layer and separated from the first interconnection layer and the second interconnection layer; wherein the warpage control member is positioned at a same level as the one of the first interconnection layer and the second interconnection layer, relative to the core layer, and is free of the first and second pads.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Kyongsoon
• KIL Myoungkyun
• Ryu Hansung

Classifications

• H05K1/0271

  Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title