Semiconductor package in package

Patent metadata

Field	Value
Publication number	US-2016379933-A1
Application number	US-201615261965-A
Country	US
Kind code	A1
Filing date	Sep 11, 2016
Priority date	Feb 21, 2007
Publication date	Dec 29, 2016
Grant date	—

Abstract

A semiconductor package having a second semiconductor package or module integrated therein. The semiconductor package of the present invention typically comprises active and passive devices which are each electrically connected to an underlying substrate. The substrate is configured to place such active and passive devices into electrical communication with contacts of the substrate disposed on a surface thereof opposite that to which the active and passive devices are mounted. The module of the semiconductor package resides within a complimentary opening disposed within the substrate thereof. The module and the active and passive devices of the semiconductor package are each fully or at least partially covered by a package body of the semiconductor package.

First claim

What is claimed is:

1 - 20 . (canceled)

21 . A semiconductor package, comprising:
a substrate having an opening extending from a substrate top surface to a substrate bottom surface, wherein the substrate has a substrate conductive pattern disposed on the substrate top surface and a plurality of contacts disposed on the substrate bottom surface, the contacts being in electrical communication with the substrate conductive pattern; an electronic component attached to the substrate top surface and electrically connected to the substrate conductive pattern; an electronic module at least partially disposed within the opening and including a plurality of module contacts and a module body defining a side surface and a top surface of the electronic module, the electronic module further comprising:
a module substrate having a module conductive pattern disposed on a module substrate top surface, the module conductive pattern comprising a module conductive pattern top surface, the plurality of module contacts disposed on a module substrate bottom surface, the plurality module contacts being in electrical communication with the module conductive pattern, the module substrate further comprising a perimeter surface, wherein the module body extends to the perimeter surface such that no portion of the module conductive pattern top surface is exposed proximate to the perimeter surface; and
an electronic module component attached to the module substrate top surface and electrically connected to the module conductive pattern, wherein the module body encloses the electronic module component;
a package body at least partially enclosing the substrate, enclosing the electronic component, and enclosing the side surface and the top surface of the electronic module such that the contacts of the substrate and the module contacts of the electronic module are exposed in a common exterior surface of the semiconductor package; and a shield structure at least laterally disposed between the electronic module component and the electronic component.

22 . The semiconductor package of claim 21 , wherein the package body physically contacts the shield structure.

23 . The semiconductor package of claim 21 , wherein the package body physically contacts top and side surfaces of the shield structure.

24 . The semiconductor package of claim 21 , wherein the shield structure is within a void disposed in the package body.

25 . The semiconductor package of claim 24 , wherein the void comprises a conical shape in cross-sectional view.

26 . The semiconductor package of claim 21 , wherein the shield structure is electrically coupled to the substrate conductive pattern.

27 . The semiconductor package of claim 21 , wherein the shield structure extends to overlie the top surface of the electronic module.

28 . The semiconductor package of claim 21 , wherein the module electronic component is disposed within the opening and disposed at least in part below the substrate top surface.

29 . The semiconductor package of claim 21 , wherein the module substrate top surface faces the substrate top surface.

30 . The semiconductor package of claim 21 further in combination with a printed circuit board having a wiring pattern disposed thereon, the wiring pattern being configured to place the module contacts of the module into electrical communication with at least some of the contacts of the substrate when the contacts and the module contacts are each electrically connected to the wiring pattern.

31 . A semiconductor package structure, comprising:
a substrate having an opening extending from a substrate top surface to a substrate bottom surface, wherein the substrate has a substrate conductive pattern disposed on the substrate top surface and a plurality of contacts disposed on the substrate bottom surface; an electronic component electrically connected to the substrate conductive pattern; an electronic module disposed within the opening and comprising a plurality of module contacts and a module body defining a side surface and a top surface of the electronic module, the electronic module further comprising:
a module substrate having a module conductive pattern disposed on a module substrate top surface, the module conductive pattern comprising a module conductive pattern top surface, the plurality of module contacts disposed on a module substrate bottom surface, the module substrate further comprising a perimeter surface, wherein the module body extends to the perimeter surface to cover the entirety of the module conductive pattern top surface proximate to the perimeter surface; and
an electronic module component electrically connected to the module conductive pattern, wherein the module body encloses the electronic module component;
a package body at least partially enclosing the substrate, enclosing the electronic component, and enclosing the side surface and the top surface of the electronic module such that the contacts of the substrate and the module contacts of the electronic module are exposed in a common exterior surface of the semiconductor package; and a shield structure at least laterally disposed between the electronic module component and the electronic component.

32 . The structure of claim 31 , wherein the package body physically contacts the shield structure.

33 . The structure of claim 31 , wherein the package body physically contacts top and side surfaces of the shield structure.

34 . The structure of claim 31 , wherein the shield structure extends to overlap the top surface of the electronic module, and wherein the shield structure is electrically coupled to the substrate conductive pattern.

35 . The structure of claim 31 , wherein the module electronic component is disposed within the opening and at least partially disposed below the substrate top surface.

36 . A semiconductor package structure, comprising:
a substrate having an opening extending from a substrate top surface to a substrate bottom surface, wherein the substrate has a substrate conductive pattern disposed on the substrate top surface and a plurality of contacts disposed on the substrate bottom surface; an electronic component electrically connected to the substrate conductive pattern; an electronic module disposed within the opening and including a plurality of module contacts and a module body defining a side surface and a top surface of the electronic module, the electronic module further comprising:
a module substrate having a module conductive pattern disposed on a module substrate top surface, the module conductive pattern comprising a module conductive pattern top surface, the plurality of module contacts disposed on a module substrate bottom surface, the module substrate further comprising a perimeter surface, wherein the module body extends to the perimeter surface such that the module conductive pattern top surface is completely covered proximate to the perimeter surface; and
an electronic module component electrically connected to the module conductive pattern, wherein the module body encloses the electronic module component;
a package body at least partially enclosing the substrate, enclosing the electronic component, and enclosing the side surface and the top surface of the electronic module such that the contacts of the substrate and the module contacts of the electronic module are exposed in a common exterior surface of the semiconductor package; and a shield structure laterally disposed between the side surface of the electronic module and the electronic component.

37 .

Assignees

• Amkor Technology Inc
• Amkor Technology Inc

Inventors

• Scanlan Christopher M
• Berry Christopher J

Classifications

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/681

  comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title