Finfet power supply decoupling

Patent metadata

Field	Value
Publication number	US-2016379928-A1
Application number	US-201514752399-A
Country	US
Kind code	A1
Filing date	Jun 26, 2015
Priority date	Jun 26, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

Embodiments herein describe dummy gates disposed over a portion of a fin in finFETs. That is, instead of separating the dummy gates from the finFET structure, the fins may be extended and covered, at least partially, by the dummy gates. An insulative material is disposed between the dummy gate and the fin in order to form a decoupling capacitor. In one embodiment, the dummy gate overlaps a portion of the fin that is held at a voltage rail. Moreover, the dummy gate may be coupled to a different (e.g., opposite) voltage rail than rail coupled to the fin. For example, if the fin is coupled to V HIGH then the dummy gate is coupled to V LOW , or vice versa. Thus, the capacitor formed using the fin and the dummy gate provides a decoupling capacitance between the power sources generating the voltage rails (i.e., V HIGH and V LOW ).

First claim

1 . A fin field effect transistor (FET) comprising:
a fin extending in a first direction on a substrate; a gate extending in a second direction on the substrate substantially perpendicular to the first direction, wherein the gate is disposed over a first portion of the fin in order to selectively activate a conductive channel in the first portion of the fin in response to a time-varying gate signal; a dummy fin structure extending in the second direction on the substrate and overlapping a second portion of the fin, wherein the dummy fin structure is coupled to a first voltage rail; a conductive contact contacting a third portion of the fin located between the first and second portions, the contact electrically coupling the third portion of the fin to a second voltage rail different from the first voltage rail; and a dielectric material disposed between the dummy fin structure and the second portion of the fin, whereby the dielectric material and second portion of the fin form a decoupling capacitance between the first and second voltage rails.

2 . (canceled)

3 . The finFET of claim 1 , wherein the first and second voltage rails are coupled to first and second DC power supplies, wherein the first DC power supply is configured to generate a first DC voltage and the second DC power supply is configured to generate a second DC voltage different from the first DC voltage.

4 . The finFET of claim 1 , wherein the dummy fin structure surrounds the second portion of the fin on at least three sides.

5 . The finFET of claim 4 , wherein the fin does not extend through the dummy fin structure.

6 . The finFET of claim 1 , further comprising:
a second fin extending in the first direction on the substrate, wherein the gates is disposed over a first portion of the second fin in order to selectively activate a conductive channel in the first portion of the second fin in response to the time-varying gate signal, and wherein the dummy fin structure overlaps a second portion of the second fin, and wherein the conductive contact couples with a third portion of the second fin that is located between the first and second portions of the second fin.

7 . The finFET of claim 1 , further comprising:
a second dummy fin structure extending in the second direction on the substrate and overlapping a fourth portion of the fin, wherein the second dummy fin structure is coupled to a second voltage rail; and a second conductive contact coupled with a fifth portion of the fin located between the first and fourth portions of the fin, the contact electrically coupling the fifth portion of the fin to a fourth voltage rail different from the third voltage rail.

8 . The finFET of claim 7 , further comprising:
a dielectric material disposed between the second dummy fin structure and the fourth portion of the fin, whereby the dielectric material and fourth portion of the fin form a decoupling capacitance between the third and fourth voltage rails.

9 . The finFET of claim 8 , wherein the second voltage rail is different from the fourth voltage rail.

10 . The finFET of claim 7 , further comprising:
a second gate extending in the second direction on the substrate substantially perpendicular to the first direction, wherein the second gate is disposed over a sixth portion of the fin in order to selectively activate a second conductive channel in the sixth portion of the fin in response to a second time-varying gate signal.

11 . An integrated circuit, comprising:
a fin extending in a first direction on a substrate; a gate extending in a second direction on the substrate substantially perpendicular to the first direction, wherein the gate is disposed over a first portion of the fin in order to selectively activate a conductive channel in the first portion of the fin in response to a time-varying gate signal; and a dummy fin structure extending in the second direction on the substrate and overlapping a second portion of the fin, wherein the dummy fin structure is coupled to a first voltage rail; and a conductive contact coupled with a third portion of the fin located between the first and second portions, the contact electrically coupling the third portion of the fin to a second voltage rail different from the first voltage rail, wherein the dummy fin structure surrounds the second portion of the fin on at least three sides, and wherein the fin does not extend through the dummy fin structure.

12 . The integrated circuit of claim 11 , further comprising:
a dielectric material disposed between the dummy fin structure and the second portion of the fin, whereby the dielectric material and second portion of the fin form a decoupling capacitance between the first and second voltage rails.

13 - 14 . (canceled)

15 . The integrated circuit of claim 11 , further comprising:
a second fin extending in the first direction on the substrate, wherein the gates is disposed over a first portion of the second fin in order to selectively activate a conductive channel in the first portion of the second fin in response to the time-varying gate signal, and wherein the dummy fin structure overlaps a second portion of the second fin, and wherein the conductive contact couples with a third portion of the second fin that is located between the first and second portions of the second fin.

16 . A method of operating a finFET, comprising:
driving a time-varying gate signal onto a gate extending in a first direction on a substrate, wherein the gate is disposed over a first portion of a fin extending in a second direction on the substrate substantially perpendicular to the first direction, and wherein the time-varying signal selectively activates a conductive channel in the first portion of the fin; while driving the time-varying gate signal, driving a first DC voltage on a dummy fin structure extending in the second direction on the substrate, the dummy fin structure overlapping a second portion of the fin; while driving the time-varying gate signal, driving a second DC voltage different from the first DC voltage on a conductive contact contacting a third portion of the fin that is located between the first and second portions; receiving the first DC voltage from a first DC power supply; and receiving the second DC voltage rail from a second DC power supply.

17 . The method of claim 16 , wherein a dielectric material is disposed between the dummy fin structure and the second portion of the fin, whereby the dielectric material and second portion of the fin form a decoupling capacitance between the first and second DC voltages.

18 . (canceled)

19 . The method of claim 16 , wherein the dummy fin structure surrounds the second portion of the fin on at least three sides.

20 . The method of claim 19 , wherein the fin does not extend through the dummy fin structure.

Assignees

• IBM

Inventors

• Christensen Todd A
• Sheets Ii John E

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/495 Primary

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H03K17/04

  Modifications for accelerating switching · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D30/6213

  having rounded corners · CPC title