Method to protect mol metallization from hardmask strip process

US2016379872A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016379872-A1
Application numberUS-201514752210-A
CountryUS
Kind codeA1
Filing dateJun 26, 2015
Priority dateJun 26, 2015
Publication dateDec 29, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method can include forming a contact trench in a semiconductor structure so that the contact trench extends to a contact formation, the forming including using a hardmask layer, and filling the contact trench with a sacrificial material layer, the sacrificial material layer formed over the contact formation. A semiconductor structure can include a sacrificial material layer over a contact formation.

First claim

Opening claim text (preview).

1 . A method comprising: forming a contact trench in a semiconductor structure so that the contact trench extends to a contact formation, the contact formation comprising a conductive material in contact with one of a separate source and drain, the forming including using a hardmask layer; filling the contact trench with a sacrificial material layer, the sacrificial material layer formed over the contact formation; removing the hardmask layer; removing the sacrificial material layer from the trench to expose the contact formation without exposing the one of a source and drain; and wherein the sacrificial material is provided by a carbon based material, and wherein the removing the sacrificial material layer includes using a plasma etch process. 2 . The method of claim 1 , wherein the filling the contact trench includes initially overfilling the contact trench with the sacrificial material layer and then recessing the sacrificial material layer. 3 . (canceled) 4 . The method of claim 1 , wherein the sacrificial material layer is provided by an oxide, and wherein the removing the sacrificial material layer includes using a wet etch process. 5 . The method of claim 1 , wherein the contact formation is a middle of the line (MOL) contact formation. 6 . The method of claim 1 , wherein the contact formation includes a first material, and wherein the hardmask layer is formed of the first material. 7 . The method of claim 1 , wherein the contact formation includes a first element and wherein the hardmask layer includes the first element. 8 . The method of claim 1 , wherein the contact formation and the hardmask layer have a common characteristic. 9 . The method of claim 1 , wherein the contact formation and the hardmask layer include conductive material. 10 . The method of claim 1 , wherein material of the contact formation is non-selective with the hardmask layer. 11 . A method comprising: forming a contact trench in a semiconductor structure so that the contact trench extends to a contact formation, the contact formation comprising a conductive material in contact with one of a separate source and drain, the forming including using a hardmask layer; filling the contact trench with a sacrificial material layer, the sacrificial material layer formed over the contact formation; removing the hardmask layer; removing the sacrificial material layer from the trench to expose the contact formation without exposing the one of a source and drain; wherein the sacrificial material layer is provided by a carbon based material, and wherein the removing sacrificial material layer includes using a plasma etch process; and wherein the contact trench is formed in an ultra low k dielectric layer. 12 . The method of claim 1 , wherein the sacrificial material layer is non-conductive. 13 . The method of claim 1 , wherein the method is used in a fabrication of a connection selected from the group consisting of a BEOL to MOL connection, a BEOL to BEOL connection, and a MOL to MOL connection. 14 . A semiconductor structure comprising: a contact formation; one or more dielectric layer formed over the contact formation; a hardmask layer formed over the one or more dielectric layer; a contact trench formed in the one or more dielectric layer, the contact trench extending to the contact formation; a sacrificial material layer formed in the contact trench over the contact formation to protect the contact formation wherein the sacrificial material layer is configured to be selective with respect to the one or more dielectric layer. 15 . (canceled) 16 . (canceled) 17 . The semiconductor structure of claim 1 , wherein the sacrificial material layer is formed of carbon based material. 18 . The semiconductor structure of claim 1 , wherein material of the contact formation and the hardmask material layer are formed of a common material. 19 . The semiconductor structure of claim 1 , wherein material of the contact formation is non-selective with the hardmask material layer. 20 . The semiconductor structure of claim 1 , wherein the sacrificial material layer is formed of non-conductive material.

Assignees

Inventors

Classifications

  • the openings being via holes penetrating underlying conductors · CPC title

  • Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

  • using masks for insulating materials · CPC title

  • by liquid etching only · CPC title

  • H10W20/077Primary

    on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

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What does patent US2016379872A1 cover?
A method can include forming a contact trench in a semiconductor structure so that the contact trench extends to a contact formation, the forming including using a hardmask layer, and filling the contact trench with a sacrificial material layer, the sacrificial material layer formed over the contact formation. A semiconductor structure can include a sacrificial material layer over a contact for…
Who is the assignee on this patent?
Globalfoundries Inc
What technology area does this patent fall under?
Primary CPC classification H10W20/077. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Dec 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).