Interconnect Structure Having an Etch Stop Layer Over Conductive Lines

Patent metadata

Field	Value
Publication number	US-2016379871-A1
Application number	US-201514751543-A
Country	US
Kind code	A1
Filing date	Jun 26, 2015
Priority date	Jun 26, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

A multilayer interconnect structure for integrated circuits includes a first dielectric layer over a substrate and a conductive line partially exposed over the first dielectric layer. The structure further includes an etch stop layer over both the first dielectric layer and the exposed conductive line, and a second dielectric layer over the etch stop layer. The second dielectric layer and the etch stop layer provide a via hole that partially exposes the conductive line. The structure further includes a via disposed in the via hole, and another conductive line disposed over the via and coupled to the conductive line through the via. Methods of forming the multilayer interconnect structure are also disclosed. The etch stop layer reduces the lateral and vertical etching of the first and second dielectric layers when the via hole is misaligned due to overlay errors.

First claim

1 . A device, comprising:
a substrate; a first dielectric layer over the substrate; a conductive line, a first portion of the conductive line laid in the first dielectric layer and a second portion of the conductive line disposed over the first dielectric layer; an etch stop layer over the first dielectric layer and on top and sidewalls of the conductive line; a second dielectric layer over the etch stop layer, wherein the etch stop layer includes a dielectric material different from materials of the first and second dielectric layers, and wherein the second dielectric layer and the etch stop layer provide an opening that partially exposes the conductive line; and a via disposed in the opening and coupled to the conductive line.

2 . The device of claim 1 , wherein the via is disposed over a top surface of the conductive line.

3 . The device of claim 1 , wherein the via is disposed over both a top surface and a sidewall surface of the conductive line.

4 . The device of claim 1 , further comprising:
another conductive line disposed over the via and coupled to the conductive line through the via.

5 . The device of claim 1 , wherein the second portion of the conductive line has rounded edges between its top surface and sidewall surfaces.

6 . The device of claim 1 , wherein the first and second dielectric layers include the same low-K dielectric material.

7 . The device of claim 1 , wherein the etch stop layer has a higher density than both the first and second dielectric layers do.

8 . The device of claim 1 , wherein the first and second dielectric layers each include a low-K dielectric material and the etch stop layer includes a material selected from: SiCN, SiCO, SiO 2 , SiN, and AlON.

9 . The device of claim 1 , wherein the etch stop layer has a conformal cross-sectional profile.

10 . A method for manufacturing a multilayer interconnect structure for integrated circuits, comprising:
providing a device that includes:
a substrate;
a first dielectric layer over the substrate; and
a conductive line laid in the first dielectric layer, wherein a top surface of the conductive line and a top surface of the first dielectric layer are coplanar;
recessing the top surface of the first dielectric layer such that a first portion of the conductive line is over the first dielectric layer; depositing an etch stop layer over in direct contact with both the first dielectric layer and the first portion of the conductive line; depositing a second dielectric layer over the etch stop layer; performing an etching process to the second dielectric layer and the etch stop layer to form a via hole that partially exposes the conductive line, wherein an etching rate of the etch stop layer in the etching process is slower than an etching rate of the second dielectric layer in the etching process; and forming a via in the via hole.

11 . The method of claim 10 , wherein the etching rate of the etch stop layer is three times slower than the etching rate of the second dielectric layer.

12 . The method of claim 10 , wherein the via hole exposes the top surface and a sidewall surface of the conductive line.

13 . The method of claim 10 , wherein the via hole exposes the top surface of the conductive line but does not expose a sidewall surface of the conductive line.

14 . The method of claim 10 , wherein the recessing of the top surface of the first dielectric layer includes reactive ion etch.

15 . The method of claim 10 , wherein the etch stop layer has a conformal cross-sectional profile.

16 . The method of claim 10 , wherein the second dielectric layer includes a low-K dielectric material and the etch stop layer includes a material selected from: SiCN, SiCO, SiO 2 , SiN, and AlON.

17 . The method of claim 10 , further comprising:
forming another conductive line over the via and coupled to the conductive line through the via.

18 . A method for manufacturing a multilayer interconnect structure for integrated circuits, comprising:
providing a device that includes:
a substrate;
a first dielectric layer over the substrate; and
a conductive line laid in the first dielectric layer, wherein a top surface of the conductive line and a top surface of the first dielectric layer are coplanar;
recessing the top surface of the first dielectric layer such that a first portion of the conductive line is exposed above the top surface of the first dielectric layer; forming an etch stop layer over the first dielectric layer and the first portion of the conductive line, the etch stop layer having a conformal cross-sectional profile; depositing a second dielectric layer over the etch stop layer, wherein the first and second dielectric layers are of the same material; etching the second dielectric layer and the etch stop layer to form a via hole that partially exposes the conductive line, wherein the etch stop layer has a slower etching rate than the second dielectric layer does; and forming a via in the via hole.

19 . The method of claim 18 , wherein the conductive line includes copper and the recessing of the top surface of the first dielectric layer includes reactive ion etch.

20 . The method of claim 18 , wherein the first and second dielectric layers include a low-K dielectric material and the etch stop layer includes a material selected from: SiCN, SiCO, SiO 2 , SiN, and AlON.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Cheng-Hsiung
• Lee Chung-Ju
• Shue Shau-Lin
• Bao Tien-I

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/084

  for dual-damascene structures · CPC title

• H10W20/081 Primary

  by forming openings in the dielectric parts · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title