Methods of a graphics-processing unit for tile-based rendering of a display area and graphics-processing apparatus

Patent metadata

Field	Value
Publication number	US-2016379336-A1
Application number	US-201615075041-A
Country	US
Kind code	A1
Filing date	Mar 18, 2016
Priority date	Apr 1, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

A method of a graphics-processing unit (GPU) for tile-based rendering of a display area and a graphics-processing apparatus are provided. The method includes the steps of computing vertex positions of a plurality of vertexes, wherein the first vertex corresponds to a first thread and the second vertex corresponds to a second thread; determining whether a thread merge condition is satisfied; merging the first thread and the second thread to a thread group when determining that the thread merge condition is satisfied; computing vertex varyings of the plurality of vertexes, wherein when the first thread and the second thread are merged to the thread group, a varying of the first vertex and a varying of the second vertex are computed with respect to a program counter.

First claim

What is claimed is:

1 . A method of a graphics-processing unit (GPU) for tile-based rendering of a display area, comprising:
computing vertex positions of a plurality of vertexes, wherein a first vertex of the plurality of vertexes corresponds to a first thread and a second vertex of the plurality of vertexes corresponds to a second thread; determining whether a thread merge condition is satisfied; merging the first thread and the second thread to a thread group when determining that the thread merge condition is satisfied; computing vertex varyings of the plurality of vertexes, wherein when the first thread and the second thread are merged to the thread group, a varying of the first vertex and a varying of the second vertex are computed with respect to a program counter, wherein the thread merge condition is satisfied if: the first thread and the second thread belong to the same draw call; or a shader code assembly of the first thread is identical to a shader code assembly of the second thread and hardware settings of the first thread are identical to hardware settings of the second thread.

2 . The graphics-processing method of claim 1 , wherein the hardware settings of the first thread and the hardware settings of the second thread each comprises at least one of the following:
shader program instruction code, primitive type, input attribute type, output varying type, uniform memory organization, mathematical precision, rounding mode, performance hint, vertex buffer base, texture format, texture filtering, application process standard application programming interface (API), and hardware global register settings.

3 . The graphics-processing method of claim 1 , wherein the first thread and the second thread belong to different draw calls or the first thread and the second thread belong to different tiles.

4 . The graphics-processing method of claim 1 , further comprising:
recording a draw call information of the first thread and the draw call information of the second thread when determining that the thread merge condition is satisfied and the first thread and the second thread belong to different draw calls.

5 . The graphics-processing method of claim 1 , further comprising:
recording tile information of the first thread and tile information of the second thread when determining that the thread merge condition is satisfied and the first thread and the second thread correspond to different tiles of the display area.

6 . The graphics-processing method of claim 1 , further comprising:
determining whether to compute the vertex varyings of the plurality of vertexes in a binning phase or in a rendering phase so as to provide a determination result, wherein computing the vertex varyings of the plurality of vertexes is in the binning phase or in the rendering phase according to the determination result.

7 . The graphics-processing method of claim 6 , wherein the varying of the first vertex is computed in either a binning phase or a rendering phase, and the varying of the second vertex is computed in the other, either the binning phase or the rendering phase, if it is determined that the thread merge condition is not satisfied; and the varying of the first vertex and the varying of the second vertex are computed in the rendering phase, if it is determined that the thread merge condition is satisfied.

8 . The graphics-processing method of claim 6 , further comprising:
recording a shading stage of the first thread and a shading stage of the second thread when determining that the thread merge condition is satisfied and the shading stage of the first thread is different from the shading stage of the second thread, wherein the shading stage of the first thread and the shading stage of the second thread each corresponds to either the binning phase or the rendering phase.

9 . A graphics-processing apparatus, comprising:
at least one vertex shader, configured to compute vertex positions of a plurality of vertexes and compute the vertex varying of the plurality of vertexes, wherein a first vertex of the plurality of vertexes corresponds to a first thread and a second vertex of the plurality of vertexes corresponds to a second thread; and a first checking unit, configured to determine whether a thread merge condition is satisfied, wherein the thread merge condition is satisfied when the first thread and the second thread belong to the same draw call or when a shader code assembly of the first thread is identical to a shader code assembly of the second thread and hardware settings of the first thread are identical to hardware settings of the second thread, a thread merge logic circuit, configured to merge the first thread and the second thread to a thread group when the thread merge condition is satisfied, wherein when the first thread and the second thread are merged to the thread group, the at least one vertex shader computes a varying of the first vertex and a varying of the second vertex with respect to a program counter.

10 . The graphics-processing apparatus of claim 9 , wherein the hardware settings of the first thread and the hardware settings of the second thread each comprises at least one of the following:
shader program instruction code, primitive type, input attribute type, output varying type, uniform memory organization, mathematical precision, rounding mode, performance hint, vertex buffer base, texture format, texture filtering, application process standard application programming interface (API), and hardware global register settings.

11 . The graphics-processing apparatus of claim 9 , wherein the first thread and the second thread belong to different draw calls or the first thread and the second thread belong to different tiles.

12 . The graphics-processing apparatus of claim 9 , further comprising:
a memory unit, configured to record the draw call information of the first thread and the draw call information of the second thread when determining that the thread merge condition is satisfied and the first thread and the second thread belong to different draw calls.

13 . The graphics-processing apparatus of claim 12 , wherein the memory unit is further configured to record tile information of the first thread and tile information of the second thread when determining that the thread merge condition is satisfied and the first thread and the second thread correspond to different tiles of the display area.

14 . The graphics-processing apparatus of claim 9 , further comprising:
a second checking unit, configured to determine whether to compute the vertex varyings of the plurality of vertexes in a binning phase or in a rendering phase so as to provide a determination result, wherein the vertex shader computes the vertex varyings of the plurality of vertexes is in the binning phase or in the rendering phase according to the determination result.

15 . The graphics-processing apparatus of claim 14 , wherein the varying of the first vertex is computed in either a binning phase or a rendering phase, and the varying of the second vertex is computed in the other, either the binning phase or the rendering phase, if it is determined that the thread merge condition is not satisfied, and the varying of the first vertex and the varying of the second vertex are computed in the rendering phase, if it is determined that the thread merge condition is satisfied.

16 . The graphics-processing apparatus of claim 14 , further comprising:
a memory unit, configured to record a shading stage of the first thread and a shading stage of the second thread when the first checking u

Assignees

• Mediatek Inc

Inventors

• Tsung Pei-Kuei
• Tsai Sung-Fang
• Liao Ming-Hao
• LIN Yang-Yao
• LIANG Ken-Fu
• Liu Chun-Shen

Classifications

• G06T11/40

  Filling planar surfaces by adding surface attributes, e.g. adding colours or textures · CPC title

• G06F9/50

  Allocation of resources, e.g. of the central processing unit [CPU] · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title

• G06T15/80

  Shading · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title