Receiver packet handling

US2016378702A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016378702-A1
Application numberUS-201615192723-A
CountryUS
Kind codeA1
Filing dateJun 24, 2016
Priority dateJun 29, 2015
Publication dateDec 29, 2016
Grant date

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Methods and devices for handling short Peripheral Component Interconnect Express (PCIe) Transaction Layer Packets (TLPs) are described. A receiver can receive at least a portion of a first packet and can process the first packet to determine if the first packet is a short packet. The receiver can receive at least a portion of a second packet and if the first packet is a short packet, the receiver can transmit a negative acknowledgement (NAK) in response to the second packet and can receive a retransmission of the second packet.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method for receiving communications packets by a receiver, the method comprising: receiving, by receiving circuitry of the receiver, at least a portion of a first packet; processing, by processing circuitry of the receiver, the first packet to determine if the first packet is of a particular packet type; receiving by the receiving circuitry of the receiver, at least a portion of a second packet; and if the first packet is of the particular packet type, transmitting, by transmitting circuitry of the receiver, a negative acknowledgement (NAK) in response to the second packet. 2 . The method of claim 1 , wherein the processing comprises determining whether the first packet passes a data link check, and the NAK is transmitted without further processing of the second packet. 3 . The method of claim 1 , further comprising receiving a retransmission of the second packet in response to the NAK. 4 . The method of claim 1 , wherein the particular packet type comprises a packet having a certain length. 5 . The method of claim 1 , wherein the particular packet type comprises a short packet, wherein a short packet is a packet of four or fewer double-words in length. 6 . The method of claim 1 , wherein the particular packet type comprises a packet which is shorter than a Peripheral Component Interconnect Express (PCIe) Transaction Layer Packet (TLP). 7 . The method of claim 1 , wherein the particular packet type comprises an improperly formed packet. 8 . The method of claim 1 , wherein the particular packet type comprises a packet which does not comply with a PCIe packet format. 9 . A receiver configured to receive communications packets, comprising: receiving circuitry configured to receive at least a portion of a first packet; processing circuitry configured to process the first packet to determine if the first packet is of a particular packet type; the receiving circuitry further configured to receive at least a portion of a second packet; and transmitting circuitry configured to transmit a negative acknowledgement (NAK) in response to the second packet if the first packet is determined to be of the particular packet type. 10 . The receiver of claim 9 , wherein the transmitting circuitry is configured to transmit the NAK without further processing of the second packet by the processing circuitry. 11 . The receiver of claim 9 , wherein the receiving circuitry is further configured to receive a retransmission of the second packet in response to the NAK. 12 . The receiver of claim 9 , wherein the particular packet type comprises a packet having a certain length. 13 . The receiver of claim 9 , wherein the particular packet type comprises a short packet. 14 . The receiver of claim 9 , wherein the particular packet type comprises a packet which is shorter than a Peripheral Component Interconnect Express (PCIe) Transaction Layer Packet (TLP). 15 . The receiver of claim 9 , wherein the particular packet type comprises a improperly formed packet. 16 . The receiver of claim 9 , wherein the particular packet type comprises a packet which does not comply with a PCIe packet format. 17 . A method for receiving communications packets by a receiver, the method comprising: receiving, by receiving circuitry of the receiver, at least a portion of a first packet; and if the first packet is received within a threshold time of an earlier received packet, transmitting, by transmitting circuitry of the receiver, a negative acknowledgement (NAK) in response to the first packet. 18 . The method of claim 17 , wherein the NAK is transmitted without further processing of the first packet. 19 . The method of claim 17 , further comprising receiving a retransmission of the first packet in response to the NAK. 20 . The method of claim 17 , wherein the first packet comprises a packet of a certain type.

Assignees

Inventors

Classifications

  • on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

  • G06F13/36Primary

    for access to common bus or bus system · CPC title

  • Physical resource allocation for ACK/NACK (for physical mapping arrangements in ARQ protocols H04L1/1861) · CPC title

  • PCI express · CPC title

  • by determining packet size, e.g. maximum transfer unit [MTU] · CPC title

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Frequently asked questions

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What does patent US2016378702A1 cover?
Methods and devices for handling short Peripheral Component Interconnect Express (PCIe) Transaction Layer Packets (TLPs) are described. A receiver can receive at least a portion of a first packet and can process the first packet to determine if the first packet is a short packet. The receiver can receive at least a portion of a second packet and if the first packet is a short packet, the receiv…
Who is the assignee on this patent?
Ati Technologies Ulc
What technology area does this patent fall under?
Primary CPC classification G06F13/36. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Dec 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).