Implementing pseudo non-masking interrupts behavior using a priority interrupt controller

Patent metadata

Field	Value
Publication number	US-2016378699-A1
Application number	US-201514876845-A
Country	US
Kind code	A1
Filing date	Oct 7, 2015
Priority date	Jun 27, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

A method is provided for handling interrupts in a processor, the interrupts including regular interrupts having a range of priorities and a pseudo non-maskable interrupt (PNMI) that is of a higher priority than any of the regular interrupts. The method includes obtaining an interrupt vector corresponding to a received interrupt, and if the received interrupt is a PNMI, executing a PNMI interrupt handler. If the received interrupt is a regular interrupt, the method further comprises reading a mask flag that indicates whether regular interrupts are enabled in an interrupt controller and further: if the mask flag indicates that regular interrupts are enabled, enabling interrupts in the processor so that a PNMI can be received while handling the regular interrupt, executing, a regular interrupt handler, and disabling interrupts in the processor; and if the mask flag indicates that regular interrupts are disabled, saving the interrupt vector for subsequent handling.

First claim

What is claimed:

1 . A method for handling interrupts in a processor, the interrupts including regular interrupts having a range of priorities and a pseudo non-maskable interrupt (PNMI) that is of a higher priority than any of the regular interrupts the method comprising:
obtaining an interrupt vector corresponding to a received interrupt; if the received interrupt is a PNMI executing a PNMI interrupt handler using the interrupt vector as an input thereto; and if the received interrupt is a regular interrupt, reading a mask flag that indicates whether regular interrupts are enabled in an interrupt controller and further
if the mask flag indicates that regular interrupts are enabled in the interrupt controller, enabling interrupts in the processor so that a PNMI can be received while handling the regular interrupt, executing a regular interrupt handler using the interrupt vector as an input thereto, and disabling interrupts in the processor; and
if the mask flag indicates that regular interrupts are disabled in the interrupt controller, saving the interrupt vector for subsequent handling.

2 . The method of claim 1 , wherein the received interrupt is determined to be a PNMI based on the interrupt vector.

3 . The method of claim 1 , further comprising:
performing an end-of-interrupt operation on the interrupt vector after handling the interrupt vector.

4 . The method of claim 1 , further comprising:
disabling regular interrupts in the interrupt controller ring execution by setting the mask flag to TRUE.

5 . The method of claim 1 , further comprising:
enabling regular interrupts in the interrupt controller by setting the mask flag to FALSE.

6 . The method of claim 5 , further comprising:
if there is a saved interrupt vector at the time of enabling the regular interrupts in the interrupt controller, handing the saved interrupt vector.

7 . The method of claim 6 , wherein handling the saved interrupt vector includes:
obtaining the saved interrupt vector from a saved-vector variable and then removing the saved interrupt vector from the variable; executing a regular interrupt handler using the saved interrupt vector as an input thereto; and performing an end-of-interrupt operation on the interrupt vector after handling the interrupt vector.

8 . A computer program product stored in a non-transitory computer readable storage medium and comprising instructions that cause a processor of a computer system to perform a method for handling interrupts, the interrupts including regular interrupts having a range of priorities and a pseudo non-maskable interrupt (PNMI) that is of a higher priority than any of the regular interrupts, the method comprising:
obtaining an interrupt vector corresponding to a received interrupt; if the received interrupt is a PNMI, executing a PNMI interrupt handler using the interrupt vector as an input thereto; and if the received interrupt is a regular interrupt, reading a mask flag that indicates whether regular interrupts are enabled in an interrupt controller and further
if the mask flag indicates that regular interrupts are enabled in the interrupt controller, enabling interrupts in the processor so that a PNMI can be received while handling the regular interrupt, executing a regular interrupt handler using the interrupt vector as an input thereto, and disabling interrupts in the processor; and
if the mask flag indicates that regular interrupts are disabled in the interrupt controller, saving the interrupt vector for subsequent handling.

9 . The computer program product of claim 8 , wherein the received interrupt is determined to be a PNMI based on the interrupt vector.

10 . The computer program product of claim 8 , wherein the method further comprises:
performing an end-of-interrupt operation on the interrupt vector after handling the interrupt vector.

11 . The computer program product of claim 8 wherein the method further comprises:
disabling regular interrupts in the interrupt controller during execution by setting the mask flag to TRUE.

12 . The computer program product of claim 8 , wherein the method further comprises:
enabling regular interrupts in the interrupt controller by setting the mask flag to FALSE.

13 . The computer program product of claim 12 , wherein the method further comprises:
if there is a saved interrupt vector at the time of enabling the regular interrupts in the interrupt controller, handing the saved interrupt vector.

14 . The computer program product of claim 13 , wherein handling the saved interrupt vector includes:
obtaining the saved interrupt vector from a saved-vector variable and then removing the saved interrupt vector from the variable; executing a regular interrupt handler using the saved interrupt vector as an input thereto; and performing an end-of-interrupt operation on the interrupt vector after handling the interrupt vector.

15 . A computer system comprising:
a bus; an interrupt controller coupled to the bus, wherein the interrupt controller receives external and software-generated interrupts, and includes a priority mask register whose contents act as a priority filter for the received interrupts, which include regular interrupts having a range of priorities and a pseudo non-maskable interrupt (PNMI) that is of a higher priority than any of the regular interrupts, and an interrupt acknowledge register, which when read provides an interrupt vector corresponding to a received interrupt, the interrupt vector being an integer number; a processor coupled to the bus, wherein the processor receives an interrupt signal from the interrupt controller when the interrupt controller receives an external or software generated interrupt; and a memory coupled to the bus and containing a program that causes the processor to; read an interrupt vector corresponding to a received interrupt; if the received interrupt is a PNMI, execute a PNMI interrupt handler using the interrupt vector as an input thereto; and if the received interrupt is a regular interrupt, read a mask flag that indicates whether regular interrupts are enabled in an interrupt controller and further
if the mask flag indicates that regular interrupts are enabled in the interrupt controller, enable interrupts in the processor so that a PNMI can be received while handling the regular interrupt, execute a regular interrupt handler using the interrupt vector as an input thereto, and disable interrupts in the processor; and
if the mask flag indicates that regular interrupts are disabled in the interrupt controller, save the interrupt vector for subsequent handling.

16 . The computer system of claim 15 , wherein the received interrupt is determined to be a PNMI based on the interrupt vector.

17 . The computer system of claim 15 , wherein the program further causes the processor to:
perform an end-of-interrupt operation on the interrupt vector after handling the interrupt vector.

18 . The computer system of claim 15 , wherein the program further causes the processor to:
disable regular interrupts in the interrupt controller during execution by setting the mask flag to TRUE.

19 . The computer system of claim 15 , wherein the program further causes the processor to:
enable regular interrupts in the interrupt controller by setting the mask flag to FALSE; and if there is a saved interrupt vector at the time of enabling the regular interrupts in the interrupt controller, handing the saved interrupt vector.

20 . The computer

Assignees

• Vmware Inc

Inventors

• Warkentin Andrei
• Khan Irfan Ulla
• Laplace Cyprien
• Tuch Harvey
• Fainkichen Alexander

Classifications

• G06F13/26 Primary

  with priority control · CPC title