Multi-page check hints for selective checking of protected container page versus regular page type indications for pages of convertible memory

Patent metadata

Field	Value
Publication number	US-2016378684-A1
Application number	US-201514751902-A
Country	US
Kind code	A1
Filing date	Jun 26, 2015
Priority date	Jun 26, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

A processor of an aspect includes at least one translation lookaside buffer (TLB) and a memory management unit (MMU). Each TLB is to store translations of logical addresses to corresponding physical addresses. The MMU, in response to a miss in the at least one TLB for a translation of a first logical address to a corresponding physical address, is to check for a multi-page protected container page versus regular page (P/R) check hint. If the multi-page P/R check hint is found, then the MMU is to check a P/R indication. If the multi-page P/R check hint is not found, then the MMU does not check the P/R indication. Other processors, methods, and systems are also disclosed.

First claim

What is claimed is:

1 . A processor comprising:
at least one translation lookaside buffer (TLB), each TLB to store translations of logical addresses to corresponding physical addresses; and a memory management unit (MMU), the MMU, in response to a miss in the at least one TLB for a translation of a first logical address to a corresponding physical address, to:
check for a multi-page protected container page versus regular page (P/R) check hint;
if the multi-page P/R check hint is found, then check a P/R indication; and
if the multi-page P/R check hint is not found, then do not check the P/R indication.

2 . The processor of claim 1 , wherein the MMU is to find the multi-page P/R check hint, and wherein the multi-page P/R check hint is to apply to a plurality of pages.

3 . The processor of claim 1 , wherein the MMU is to find the multi-page P/R check hint, and wherein the multi-page P/R check hint is to apply to an entire logical address space of a process that is to correspond to the first logical address.

4 . The processor of claim 1 , wherein the MMU is to find the multi-page P/R check hint in one of a page directory base register, a core control register, and a processor context switch state save area.

5 . The processor of claim 1 , wherein the MMU is to find the multi-page P/R check hint, and wherein the multi-page P/R check hint is to apply to a logical address range which is to be a subset of an entire logical address range of a process that is to correspond to the first logical address.

6 . The processor of claim 1 , wherein the MMU is to find the multi-page P/R check hint in a hierarchical paging structure that is to be at a hierarchical level between a page directory base register and a page table.

7 . The processor of claim 6 , wherein the multi-page P/R check hint is to be stored in a page directory table.

8 . The processor of claim 6 , wherein the multi-page P/R check hint is to be stored in a page directory pointer table.

9 . The processor of claim 6 , wherein the multi-page P/R check hint is to be stored in one of a directory of page directory pointer tables entry, a page-directory-pointer table (PDPT) entry, and a page-directory table (PD) entry.

10 . The processor of claim 1 , wherein the MMU is to find the multi-page P/R check hint, and wherein the MMU is to check the P/R indication which is to be an EPCM.E bit in an enclave page cache map (EPCM).

11 . The processor of claim 1 , wherein the MMU is to check for the multi-page P/R check hint which is to indicate whether the MMU is to check for the P/R indication of whether a page corresponding to the first logical address is a regular page or a secure enclave page.

12 . The processor of claim 1 , wherein the MMU is to:
if the multi-page P/R check hint is found, store an indication of whether a page corresponding to the first logical address is a protected container page, as indicated by the P/R indication, in a TLB entry in the at least one TLB; and if the multi-page P/R check hint is not found, store an indication that the page is a regular page in the TLB entry.

13 . The processor of claim 1 , wherein the MMU is to find the multi-page P/R check hint, and further comprising a memory access unit and a memory encryption and decryption unit, wherein:
the memory encryption and decryption unit is to access a page corresponding to the first logical address if the P/R indication is to indicate that the page is a protected container page; and the memory access unit is to access the page, bypassing the memory encryption and decryption unit, if the P/R indication is to indicate that the page is a regular page.

14 . The processor of claim 1 , further comprising at least one model specific register, and wherein the processor is to determine at least one location where the MMU is to check for the P/R check hint in the at least one model specific register.

15 . An apparatus to manage pages comprising:
a protected container page versus regular page conversion module, the conversion module to convert protected container pages to regular pages, and to convert regular pages to protected container pages; and a multi-page protected container page versus regular page (P/R) check hint module communicatively coupled with the conversion module, the multi-page P/R check hint module to store a multi-page P/R check hint, wherein the multi-page P/R check hint is to provide a hint to a processor of whether the processor is to check P/R indications for multiple pages.

16 . The apparatus of claim 15 , wherein the multi-page P/R check hint module is to store the multi-page P/R check hint which is to apply to an entire logical address space of a process.

17 . The apparatus of claim 15 , wherein the multi-page P/R check hint module is to store the multi-page P/R check hint which is to apply to a logical address range that is to be a subset of an entire logical address range of a process.

18 . The apparatus of claim 15 , wherein the multi-page P/R check hint module is to store the multi-page P/R check hint in one of a page directory base register and a hierarchical paging structure that is to be at a hierarchical level between the page directory base register and a page table.

19 . The apparatus of claim 15 , wherein the conversion module comprises a protected container page grouper module to group protected container pages in pages hierarchically below an entry in a set of hierarchical paging structures, and wherein the multi-page P/R check hint module is to store the multi-page P/R check hint in the entry.

20 . An article of manufacture comprising a non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium storing instructions that if executed by a machine are to cause the machine to perform operations comprising:
convert pages between protected container pages and regular pages; and provide a multi-page protected container page versus regular page (P/R) check hint to a processor, wherein the multi-page P/R check hint is to hint to the processor to check P/R indications for multiple pages.

21 . The article of manufacture of claim 20 , wherein the instructions to provide the multi-page P/R check hint comprise instructions that if executed by the machine are to cause the machine to provide the multi-page P/R check hint which is to apply to an entire logical address space of a process.

22 . The article of manufacture of claim 20 , wherein the instructions to provide the multi-page P/R check hint comprise instructions that if executed by the machine are to cause the machine to store the multi-page P/R check hint in one of a page directory base register and a hierarchical paging structure selected from a page directory table and a page directory pointer table.

23 . The article of manufacture of claim 20 , wherein the storage medium further stores instructions that if executed by the machine are to cause the machine to perform operations comprising grouping protected container pages in pages hierarchically below an entry in a set of hierarchical paging structures.

24 . A system to process instructions comprising:
an interconnect; a dynamic random access memory (DRAM) coupled with the interconnect, the DRAM storing instructions that if executed by the system are to cause the system to perform operations comprising providing a multi-page protected container page versus regular page (P/R) check hint; and a processor

Assignees

• Intel Corp

Inventors

• Zmudzinski Krystof C
• Shanbhogue Vedvyas

Classifications

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G11C7/1072

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G06F2212/305

  being part of a memory device, e.g. cache DRAM · CPC title

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F2212/684

  TLB miss handling · CPC title