Hybrid Tracking of Transaction Read and Write Sets

US2016378673A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016378673-A1
Application numberUS-201514830108-A
CountryUS
Kind codeA1
Filing dateAug 19, 2015
Priority dateJun 24, 2015
Publication dateDec 29, 2016
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Embodiments of the invention relate to tracking processor transactional read and write sets, thereby eliminating speculative mispredictions. Both non-speculative read set and write set indications are maintained for a transaction. The indications are stored in cache. In addition, load and write queues of addresses are maintained. The load queue of addresses relates to speculative members of a read set and the write queue of addresses relates to speculating member of a write set. For a received read request, a transaction resolution process takes place, and a resolution is performed if an address match in the write queue is detected. Similarly, for a receive write request the transaction interference additionally checks the load queue and the non-speculative read set for the pending address.

First claim

Opening claim text (preview).

We claim: 1 . A computer implemented method for tracking of processor transactional read and write sets comprising: maintaining a non-speculative read set indication of non-speculative reads of data stored in a cache by a processor cache unit for a transaction by a first requestor; maintaining a non-speculative write set indication of non-speculative writes of written data stored in the cache by the processor cache unit by the first requestor; maintaining a first queue of addresses corresponding to speculatively executed memory read instructions corresponding to speculative members of a read set; maintaining a second queue of addresses corresponding to speculatively executed memory write instructions corresponding to speculative members of a write set; performing a transaction interference resolution responsive to receiving a request for data by a remote processor, including determining a potential transaction interference exclusively conflicting with a speculative instruction; and holding a response to the received request until the speculative instruction is in a state selected from the group of: committed and flushed. 2 . The method of claim 1 , further comprising: responsive to determining an instruction is next to complete, removing an entry corresponding to the instruction from a pending queue representing speculative accesses; and updating one of the non-speculative read set indication and the non-speculative write set indication. 3 . The method of claim 2 , wherein the update of the non-speculative read and write set are deferred until execution of the instructions is committed. 4 . The method of claim 1 , wherein the received request is a write request, further comprising the transaction interference additionally checking the memory read pending address queue and the non-speculative read set for interference with the requested address. 5 . The method of claim 1 , wherein the memory read queue and the memory write queue maintain an order of the addresses. 6 . The method of claim 5 , wherein the addresses being added to the queue are responsive to the speculative execution of a memory read or write instruction. 7 . The method of claim 1 , further comprising responsive to a flushing of an instruction corresponding to at least one entry in one of a read and write pending address queue, removing the at least one corresponding entry from one of a read and write pending address queue. 8 . The method of claim 7 , further comprising flushing all instructions subsequent to the flushing of the instruction, and removing any queue entries corresponding to the subsequent instructions.

Assignees

Inventors

Classifications

  • Synchronisation or serialisation instructions · CPC title

  • Casings or accessories specially adapted for storing or handling solid or pasty toiletry or cosmetic substances, e.g. shaving soaps or lipsticks (features common to containers for handling powdery or liquid toiletry or cosmetic substances A45D33/00-A45D37/00; cosmetic or like preparations A61K8/00, A61Q; sample tables or the like G09F5/00) · CPC title

  • with multilevel cache hierarchies · CPC title

  • using a soft material and a rigid material, e.g. making articles with a sealing part · CPC title

  • to perform operations on memory · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2016378673A1 cover?
Embodiments of the invention relate to tracking processor transactional read and write sets, thereby eliminating speculative mispredictions. Both non-speculative read set and write set indications are maintained for a transaction. The indications are stored in cache. In addition, load and write queues of addresses are maintained. The load queue of addresses relates to speculative members of a r…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification B29C45/1676. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Thu Dec 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).